View ISL8274MAIRZ_9083440.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn8931 rev.1.00 page 1 of 81 jan 4, 2018 fn8931 rev.1.00 jan 4, 2018 isl8274m 30a/30a dual-channel digital pmbus step-down power module datasheet the isl8274m is a complete pmbus enabled dc/dc, dual-channel, step-down adv ance power supply, capable of delivering up to 30a per channel and optimized for high power density applications. operating across an input voltage range of 4.5v to 14v, the isl8274m offers adjustable output voltages down to 0.6v and achieves up to 95.5% conversion efficiencies. a unique chargemode? control architecture provides a single clock cycle response to an output load step and can support switching frequencies up to 1.06mhz. the power module integrates all power and most passive components and requires only a few external components to operate. a set of optional external resistors allows the user to easily configure the device for standard operation. for advanced configurations, a standard pmbus interface addresses tasks such as sequencing and f ault management, as well as real-time full telemetry and point-of-load monitoring. additionally, the nonvolatile memory can store the desired custom configuration and settings. a fully customizable voltage , current, and temperature protection scheme ensures saf e operation for the isl8274m under abnormal operating cond itions. the device is also supported by the powernavigator ? software, a full digital power train development environment. the isl8274m is available in a low profile, compact 18mmx23mmx7.5mm fully encapsulated, thermally enhanced hda package. applications ? server, telecom, storage, and datacom ? industrial/ate and networking equipment ? general purpose power for asic, fpga, dsp, and memory features ? complete digital power supply ? 30a/30a dual-channel output current ? 4.5v to 14v single rail input voltage ? up to 95.5% efficiency ? programmable output voltage ? 0.6v to 5v output voltage settings ? 1.2% accuracy over li ne/load/temperature ? chargemode control loop architecture ? 296khz to 1.06mhz fixed switching frequency operations ? no compensation required ? fast single clock cycle transient response ? pmbus interface and/or pin-strap mode ? fully programmable through pmbus ? pin-strap mode for standard settings ? real-time telemetry for v in , v out , i out , temperature, duty cycle, and f sw ? advanced soft-start/stop, s equencing, and tracking ? internal nonvolatile memory ? complete over/undervoltage, current, and temperature protections with fault logging ? powernavigator supported ? thermally enhanced 18mmx23mmx7.5mm hda package related literature ? for a full list of related documents, visit our website ? isl8274m product page
fn8931 rev.1.00 page 2 of 81 jan 4, 2018 isl8274m figure 1. application circuit figure 2. small package for high power density note: this figure represents a typica l implementation of the isl8274m. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. 9,1 9'' 95 95 95 9287 6*1' 3*1' 95 9'59 6&/ 6'$ 6$/57 9021 9&& 9'59 96(13 96(11 9,1 &,1 ,6/0 9287 30%86 ,17(5)$&( &287 n n [?) ?) ?) ?? ?? en1 enable1 vout2 vsenp2 vsenn2 vout2 cout2 sa en2 enable2 2 3 m m 1 8 m m 7.5mm
fn8931 rev.1.00 page 3 of 81 jan 4, 2018 isl8274m contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 isl8274m internal block di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 thermal information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 recommended operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 efficiency performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 startup and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 derating curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 transient response performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 smbus communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 soft-start, stop delay, a nd ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7 output overcurrent prote ction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.8 loop compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.9 smbus module address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.11 output prebias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.12 thermal overload protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.13 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.14 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.15 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.16 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.17 monitoring using smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.18 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.19 nonvolatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. layout guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 thermal considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
fn8931 rev.1.00 page 4 of 81 jan 4, 2018 isl8274m 5.3 pcb layout pattern design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 thermal vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6. pmbus command summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 pmbus data formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 pmbus use guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7. pmbus commands descriptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8. firmware revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9. package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
fn8931 rev.1.00 page 5 of 81 jan 4, 2018 isl8274m 1. overview 1. overview 1.1 typical application circuits figure 3. isl8274m digital pmbus m odule dual 30a/30a application with pinstrap settings notes: 1. r 2 and r 3 are not required if the pmbus host already has i 2 c pull-up resistors. 2. only one r 4 per ddc bus is required when mul tiple modules share the same d dc bus. 3. r 7 through r 13 can be selected according to the tables for the pin-strap resi stor setting in this document. if the pmbus configuration is chosen to overwrite the pin-strap configuration, r 8 through r 13 can be non-populated. 4. v25, vr, and vr55 do not need external capacitors. v25 can be no connection. vin vdd vr55 vr5 vr vout2 sgnd pgnd vr6 vdrv scl sda salrt vmon vcc vdrv1 vsenp2 vsenn2 vin vcc isl8274m vout2 1.5v 30a 10f 10f 10f sa/cfg vset1 en2 vset2 ss/track ascr1 vaux or vcc 3.3v to 5v should be active before enable ddc sync/ocp swd1 sw1 4.5v to 14v 10f 2x470f bulk 8x22 f + 4x47f ceramic 12x100f ceramic 1x470 f poscap scl pin strap resistors (optional) en2 sda salrt ddc c 1 c 2 c 3 c 4 c 5 c 6 c 7 10f c 8 c 9 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 pg2 pg2 10k ?? 10k ?? 10k ?? 10k ?? 100k ?? 6.65k ?? r 13 ascr2 en1 en1 pg1 pg1 swd2 sw2 vout1 vout1 1.5v 30a 12x100f ceramic 1x470f poscap c 8 c 9 vsenn1 vsenp1 vtrkn vtrkn vtrkp vtrkp (note 1) (note 2) (note 3)
fn8931 rev.1.00 page 6 of 81 jan 4, 2018 isl8274m 1. overview 1.2 isl8274m internal block diagram figure 4. internal block diagram digital controller pgnd sgnd vset1/2 scl salrt sa/cfg en1/2 pg1/2 sync/ ocp sgnd pwm2 pmbus/i 2 c interface sda adc csa vsa1/2 supervisor internal temp sensor protection oc/uc d-pwm pll sync out power management ss margining ov/uv current share interleave sequence nvm vdd ddc snapshot fault spreading ot/ut vout2 0.19h logic vin pgnd vin vdrv vr6 vsen1/2p vmon adc vr5 v25 ldos vr55 vdd filter vout1 0.19h logic vin pgnd csa chargemode control adc pwm1 vr vdrv1 vdrv1 vdrv vdrv vcc ss/track ascr1/2 vdrv1 swd2 sw2 swd1 sw1 vsen1/2n 100 100 ldo adc vout1/2 vsa vtrkp vtrkn
fn8931 rev.1.00 page 7 of 81 jan 4, 2018 isl8274m 1. overview 1.3 ordering information part number ( notes 5 , 6 , 7 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # ISL8274MAIRZ isl8274ma -40 to +85 58 ld 18x23 hda module y58.18x23 isl8274meval1z evaluation board notes: 5. add -t suffix for 100 unit tape and reel option. refer to tb347 for details on reel specifications. 6. these pb-free plastic packaged products are rohs compliant by eu exemption 7c-i and 7a. they employ special pb-free material sets; molding compounds /die attach materials and nipda u plate-e4 termination finish, which is compatible with both snpb and pb-free soldering operations. pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 7. for moisture sensitivity level (msl), see the product informa tion page for the isl8274m . for more information on msl, see tb363 . table 1. key differences between family of parts part description v in range (v) v out range (v) i out (a) isl8274m digital dc/dc pmbus dual channel 30a/30a module 4.5 - 14 0.6 - 5.0 30/30 isl8272m digital dc/dc pmbus single channel 50a module 4.5 - 14 0.6 - 5.0 50 isl8273m digital dc/dc pmbus single channel 80a module 4.5 - 14 0.6 - 2.5 80 zl9024m digital dc/dc pmbus single channel 33a module 2.75-4 0.6 - 1.5 33 isl xxxxm f t r z s intersil device designator base part number firmware revision a: g0100 operating temperature i: industrial (-40c to +85c) shipping option blank: bulk -t: tape and reel rohs z: rohs compliant package designator r: high density array (hda)
fn8931 rev.1.00 page 8 of 81 jan 4, 2018 isl8274m 1. overview 1.4 pin configuration isl8274m (58 ld hda) top view a b c d e f g h j k l m n p r t u v w y aa ab ac 1 2 3 4 5 6 7 8 9 101112131415161718 pad1 pad2 pad8 pad9 pad10 pad11 pad12 pad6 pad13 pad14 pad15 pad16 pad3 pad4 pad5 pad7 vout1 vout2 pgnd pgnd pgnd pgnd pgnd pgnd sgnd pgnd pgnd sw1 sw2 vin vin vin vdrv1 vdrv1 swd2 vdrv pgnd pgnd swd1 vr vcc vsen1p vsen1n vtrkp vtrkn ddc ss/track pg1 vset1 vset2 ascr2 ascr1 sa/cfg salrt sda scl vmon sync/ocp en2 en1 vsen2p vsen2n v25 pg2 sgnd vdd vr5 sgnd vr6 vdrv pgnd vr55
fn8931 rev.1.00 page 9 of 81 jan 4, 2018 isl8274m 1. overview 1.5 pin descriptions pin number pin name type description pad1 vout1 pwr power supply output voltage. channel 1 provides an output voltage from 0.6v to 5v. refer to the functional description on page 21 to set the maximum output current from these pads. pad2 vout2 pwr power supply output voltage. channel 2 provides an output voltage from 0.6v to 5v. refer to the functional description on page 21 to set the maximum output current from these pads. pad3, pad4, pad5, pad7, pad10, pad12, pad13, pad15 pgnd pwr power ground. refer to the layout guide on page 33 for the pgnd pad connections and i/o capacitor placement. pad6 sgnd pwr signal ground. refer to layout guide on page 33 for the sgnd pad connections. pad8, pad9, pad11 vin pwr input power supply voltage to power the module. input vol tage ranges from 4.5v to 14v. pad14 sw1 pwr switching node pads for channel 1. the sw1 pad is us ed to dissipate the heat and provide the good thermal performance. refer to layout guide on page 33 for the sw1 pad connections. pad16 sw2 pwr switching node pads for channel 2. the sw2 pad is us ed to dissipate the heat and provide the good thermal performance. refer to layout guide on page 33 for the sw2 pad connections. c5 vset2 i output voltage selection pin for channel 2. used to set vout2 set point and vout2 max. c6 vset1 i output voltage selection pin for channel 1. used to set vout1 set point and vout1 max. c7 ascr2 i chargemode control ascr parameters selecti on pin for channel 2. used to se t ascr gain and residual values. c8 ascr1 i chargemode control ascr parameters selecti on pin for channel 1. used to se t ascr gain and residual values. c9 vmon i driver voltage monitoring. use this pin to monitor vdrv through an external 16:1 resistor divider. c10 sa/cfg i serial address selection pin. used to assign unique a ddress for each indi vidual device or to enable certain management features . this pin also sets the uvlo level. c11 salrt o serial alert. connect to external host if desired. sal rt is asserted low upon a warning or a fault event and deasserted when warning or fault is cleared. a pull-u p resistor is required. c12 sda i/o serial data. connect to external host and/or to other digital-dc? devices. a pull-up resistor is required. c13 scl i/o serial clock. connect to external host and/or to other digital-dc devices. a pull-up resistor is required. d4 ss/ track i soft-start/stop selection pin. used to set turn on/off delay a nd ramp time as well as tracking configuration. d5 pg1 o power-good output for channel 1. power-good output can be an open drain that requires a pull-up resistor or push-pull output t hat can drive a logic input. d13 sync/ ocp i/o clock synchronization input and ocp setting pin. used to set the frequency of the internal switch clock, to sync to an external c lock or to output internal clock . if external synchronization is used, the external clock must be active before enable. different ocp level can be set with this pin. d14 en2 i enable pin for channel 2. logic high to enable the modul e output. e14 en1 i enable pin for channel 1. logic high to enable the modul e output. e4 ddc i/o a digital-dc bus. this dedicated bus provides the commu nication between devices for features such as sequencing, fault spread ing and current sharing. the dd c pin on all digital-dc devices should be connected together. a pull-up resistor is required. e15 vsen2p i differential output voltage sense feedback for channe l 2. connect to positive output regulation point. f4 vtrkp i tracking sense positive input. used to track an externa l voltage source. f15 vsen2n i differential output voltage sense feedback for channe l 2. connect to negative output regulation point.
fn8931 rev.1.00 page 10 of 81 jan 4, 2018 isl8274m 1. overview g4 vtrkn i tracking sense negative input (return). g14 pg2 o power-good output for channel 2. power-good output can b e an open drain that requires a pull-up resistor or push-pull output t hat can drive a logic input. g15 v25 pwr internal 2.5v reference used to power internal circuit ry. no external capacitor required for this pin. not recommended to power external circuits. h3 vsen1n i differential output voltage sense feedback for channel 1. connect to a negative output regulation point. h4 vsen1p i differential output voltage sense feedback for channel 1. connect to a positive output regulation point. h16, j16, k16, m14 sgnd pwr signal grounds. use multi ple vias to connect the sgnd pi ns to the internal sgnd layer. k14 vdd pwr input supply voltage for controller. connect vdd pad t o vin supply. l2 vr pwr internal ldo bias pin. tie vr to vr55 directly with a sh ort loop trace. not recommended to power external circuits. l3 swd1 pwr switching node drivin g pins for channel 1. directly co nnect to the sw1 pad with short loop wires. p11 swd2 pwr switching node driving pins for channel 2. directly c onnect to the sw2 pad with short loop wires. l14 vr5 pwr internal 5v reference used to power internal circuitry . place a 10f decoupling capacitor for this pin. maximum external loading current is 5ma. m1 vcc pwr internal ldo output. connect vcc to vdrv for internal l do driving. m5, m17, n5 pgnd pwr power grounds. using multiple vias to connect the pgnd pins to the internal pgnd layer. m10 vr55 pwr internal 5.5v bias voltage for internal ldo use only. tie vr55 pin directly to the vr pin. not recommended to power external circuit. m13 vr6 pwr internal 6v reference used to power internal circuitry . place a 10f decoupling capacitor for this pin. not recommended to power external circuit. n6, n16 vdrv pwr power supply for internal fet drivers. connect a 10f bypass capacitor to each of these pins. these pins can be driven by the internal ldo through vcc pin or by the external power supply directly. keep the driving voltage between 4.5v and 5.5v. for 5 v input application, use external supply or connect this pin to vin. r8, r17 vdrv1 i bias pin of the inte rnal fet drivers. always tie t o vdrv. table 2. isl8274m design guide matr ix and output voltage response v out (v) i out (a) avg ocp (a) cout_bulk (f) cout_ceramic (f) ascr gain ascr residual peak-to-peak (mv) frequency (khz) 5 25 30 1*470 6*100 275 100 170 1067 5 20 25 1*470 6*100 175 80 150 615 3.3 25 30 1*470 8*100 300 90 150 800 3.3 20 25 1*470 8*100 175 80 140 571 2.5 30 35 1*470 9*100 600 100 110 1067 2.5 25 30 1*470 9*100 350 100 120 615 2.5 20 25 1*470 9*100 175 90 100 471 1.8 30 35 1*470 12*100 600 100 90 889 1.8 25 30 1*470 12*100 250 100 100 421 1.8 20 25 1*470 12*100 200 100 100 364 1.5 30 35 1*470 12*100 525 90 90 889 1.5 25 30 1*470 12*100 250 100 90 421 pin number pin name type description
fn8931 rev.1.00 page 11 of 81 jan 4, 2018 isl8274m 1. overview 1.5 20 25 1*470 12*100 140 90 100 320 1.2 30 35 1*470 12*100 600 110 70 727 1.2 25 30 4*470 12*100 250 80 60 296 1 30 35 1*470 12*100 450 110 80 615 1 25 30 5*470 12*100 250 80 50 296 0.6 30 35 7*470 12*100 300 90 50 296 notes: 8. 2x470f (eee-1ea471p) and 12x22f (grm32er71e226ke15l) are us ed for all conditions in the evaluation board. 9. 100f (grm31cd80j107me39l) ceram ic and 470f (6tpf470mah) are selected for output capacitor in the evaluation board. 10. peak-to-peak v out deviation is measured under 50%- 100% load transient while 12v input applied. 11. ascr gain and residual was designed to achieve 50 phase mar gin over temperature. (ambient temperature from -40c to +85c). 12. frequency is selected to achieve the highest efficiency at f ull load as well as avoid saturation of the inductor. for insta nce, select 615khz instead of 296khz if 1v, 26a is required to avoid inductor saturation. although be tter efficiency is obtained at 296khz supporting 1v, 25a, higher frequency can be selected bec ause less output capacitance is required to meet the transient response specification. table 2. isl8274m design guide matrix and output voltage response (continued) v out (v) i out (a) avg ocp (a) cout_bulk (f) cout_ceramic (f) ascr gain ascr residual peak-to-peak (mv) frequency (khz)
fn8931 rev.1.00 page 12 of 81 jan 4, 2018 isl8274m 2. specifications 2. specifications 2.1 absolute maximum ratings note: 13. do not apply dc voltage higher than 17v to the pins. caution: do not operate at or near the maximum ratings listed f or extended periods of time. ex posure to such conditions may adversely impact product reliabi lity and result in failures not covered by warranty. 2.2 thermal information 2.3 recommended operation conditions parameter minimum maximum unit input supply voltage, vin pin -0.3 17 v input supply voltage for controller, vdd pin -0.3 17 v mosfet switch node voltage, sw1/2, swd1/2 ( note 13 )-0.3 25v mosfet driver supply voltage, vdrv, vdrv1 pin -0.3 6.0 v output voltage, vout1/2 pin -0.3 6.0 v internal reference supply voltage vr6 pin -0.3 6.6 v vr, vr5, vr55 pin -0.3 6.5 v v25 pin -0.3 3 v logic i/o voltage for ddc, en1/2, pg1/2, ascr1/2, sa/cfg, scl, sda, salrt, sync/ocp, ss/track, vmon, vset1/2 -0.3 6.0 v analog input voltages vsen1p, vsen2p, vtrkp -0.3 6.0 v vsen1n, vsen2n, vtrkn -0.3 0.3 v esd rating value unit human body model (tested per js-001-2014) 2 kv machine model (tested per jesd22-a115c) 200 v charged device model (tested per js-002-2014) 750 v latch-up (tested per jesd78e; class 2, level a) 100 ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 58 ld hda package ( notes 14 , 15 )5.3 1.1 notes: 14. ? ja is defined by simulation in free air with the module mounted o n an 8-layer evaluation board 4.7x 4.8inch in size with 2oz cu on all layers. 15. for ? jc , the case temp location is the center of the package undersi de. parameter minimum maximum unit maximum junction temperature (plastic package) +125 c storage temperature range -55 +150 c pb-free reflow profile see figure 33 parameter minimum maximum unit input supply voltage range, v in 4.5 14 v input supply voltage range for controller, v dd 4.5 14 v output voltage range, v out 0.6 5 v output current range, i out(dc) per channel (note 18) 030a operating junction temperature range, t j -40 +125 c
fn8931 rev.1.00 page 13 of 81 jan 4, 2018 isl8274m 2. specifications 2.4 electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwi se noted. typical values are a t t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 16) typ max (note 16) unit input and supply characteristics input supply current for controller i dd v in = v dd = 12v, v out = 0v, module not enabled 40 50 ma 6v internal reference supply voltage v r6 5.5 6.1 6.6 v 5v internal reference supply v r5 i vr5 < 5ma 4.5 5.2 5.5 v 2.5v internal reference supply v 25 2.25 2.5 2.75 v internal ldo output voltage v cc 5.3 v internal ldo output current i vcc v in = v dd = 12v, v cc connected to vdrv, module enabled 50 ma input supply voltage for controller read back resolution v dd_read_res 20 mv input supply voltage for controller read back total error (note 19) v dd_read_err pmbus read 2 % fs output characteristics output voltage adjustment range v out_range 0.54 5.5 v output voltage set-point resolution v out_res configured using pmbus 0.025 %v out output voltage set-point accuracy ( notes 17 , 19 ) v out_accy includes line, load, and temperature (-20c t a +85c) -1.2 1.2 % output voltage read back resolution v out_read_res 0.15 % fs output voltage read back total error (note 19) v out_read_err pmbus read -2 2 % fs output ripple voltage v out_ripple v out = 1.5v, c out = 1 x 470f poscap + 12 x 100f ceramic 1% output current read back resolution i out_read_res isense_config default setting 0.2 a output current range (note 18) i out_range per channel 30 a output current read back total error i out_read_err pmbus read at max load v out = 1.5v 3 a soft-start and sequencing delay time from enable to v out rise t on_delay configured using pmbus 2300 ms t on_delay accuracy t on_delay_accy 2 ms output voltage ramp-up time t on_rise configured using pmbus 0.5 120 ms output voltage ramp-up time accuracy t on_rise_accy 250 s delay time from disable to v out fall t off_delay configured using pmbus 2300 ms t off_delay accuracy t off_delay_accy 2 ms
fn8931 rev.1.00 page 14 of 81 jan 4, 2018 isl8274m 2. specifications output voltage fall time t off_fall configured using pmbus 0.5 120 ms output voltage fall time accuracy t on_fall_accy 250 s power-good power-good delay v pg_delay configured using pmbus 05000 ms temperature sense temperature sense range t sense_range configurable using pmbus -50 150 ? c internal temperature sensor accuracy int_temp accy tested at +100c -5 5 ? c fault protection v dd undervoltage threshold range v dd_uvlo_range measured internally 4.18 16 v v dd undervoltage threshold accuracy (note 19) v dd_uvlo_accy 2 %fs v dd undervoltage response time v dd_uvlo_delay 10 s v out overvoltage threshold range v out_ov_range factory default 1.15v out v configured using pmbus 1.05v out v out_max v v out undervoltage threshold range v out_uv_range factory default 0.85v out v configured using pmbus 0 0.95v out v v out ov/uv threshold accuracy (note 17) v out_ov/uv_accy -2 2 % v out ov/uv response time v out_ov/uv_delay 10 s output current limit set-point accuracy (note 19) i limit_accy tested at iout_avg_oc_fault_limit = 35a 10 % fs over-temperature protection threshold (controller junction temperature) t junction factory default 115 ? c configured using pmbus -40 115 ? c thermal protection hysteresis t junction_hys 15 ? c oscillator and switching characteristics switching frequency range f sw_range 296 1067 khz switching frequency set-point accuracy f sw_accy -5 5 % minimum pulse width required from external sync clock ext_sync pw measured at 50% amplitude 150 ns drift tolerance for external sync clock ext_sync drift external sync clock equal to 500khz is not supported -10 10 % v in = v dd = 12v, t a = -40c to +85c, unless otherwi se noted. typical values are a t t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 16) typ max (note 16) unit
fn8931 rev.1.00 page 15 of 81 jan 4, 2018 isl8274m 2. specifications logic input/output characteristics bias current at the logic input pins i logic_bias ddc, en1/2, pg1/2, sa/cfg, scl, sda, ascr1/2, ss/track, salrt, sync/ocp, v mon , v set1/2 -100 +100 na logic input low threshold voltage v logic_in_low 0.8 v logic input high threshold voltage v logic_in_high 2.0 v logic output low threshold voltage v logic_out_low 2ma sinking 0.5 v logic output high threshold voltage v logic_out_high 2ma sourcing 2.25 v pmbus interface timing characteristic pmbus operating frequency f smb 100 400 khz notes: 16. compliance to datasheet limits is assured by one or more met hods: production test, characterization, and/or design. control ler is independently tested before module assembly. 17. v out measured at the termination of the vsen1/2p and vsen1/2n sense points. 18. the max load current is determined by the thermal derating curves on page 20 . 19. fs stands for full scale of recommended maximum operation range. v in = v dd = 12v, t a = -40c to +85c, unless otherwi se noted. typical values are a t t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 16) typ max (note 16) unit
fn8931 rev.1.00 page 16 of 81 jan 4, 2018 isl8274m 3. typical performance curves 3. typical performance curves 3.1 efficiency performance operating condition: t a = +25c, no air flow. c out = 1 x 470f poscap + 12 x 100f ceramic. typical values are us ed unless otherwise noted. the efficiency curves wer e measured on the evaluation bo ard. for test conditions, refer to table 2 on page 10 . figure 5. single channel eff iciency vs output current figure 6. single channel efficiency vs output current figure 7. single channel eff iciency vs output current figure 8. single channel efficiency vs output current figure 9. single channel eff iciency vs output current figure 10. single channel efficiency vs output current 65 70 75 80 85 90 95 0 5 10 15 20 25 30 efficiency (%) load current (a) 0.6v_296khz 1v_615khz 1.2v_727khz 1.5v_889khz 1.8v_889khz 2.5v_1067khz 12v in 65 70 75 80 85 90 95 0 5 10 15 20 25 efficiency (%) load current (a) 1v_296khz 1.2v_296khz 1.5v_421khz 1.8v_421khz 2.5v_615khz 3.3v_800khz 5v_1067khz 12v in 65 70 75 80 85 90 95 100 0 5 10 15 20 efficiency (%) load current (a) 1.5v_320khz 1.8v_364khz 2.5v_471khz 3.3v_571khz 5v_615khz 12v in 65 70 75 80 85 90 95 0 5 10 15 20 25 30 efficiency (%) load current (a) 0.6v_296khz 1v_615khz 1.2v_727khz 1.5v_889khz 1.8v_889khz 2.5v_1067khz 5v in 65 70 75 80 85 90 95 0 5 10 15 20 25 efficiency (%) load current (a) 1v_296khz 1.2v_296khz 1.5v_421khz 1.8v_421khz 2.5v_615khz 3.3v_800khz 5v in 65 70 75 80 85 90 95 100 0 5 10 15 20 efficiency (%) load current (a) 1.5v_320khz 1.8v_364khz 2.5v_471khz 3.3v_571khz 5v in
fn8931 rev.1.00 page 17 of 81 jan 4, 2018 isl8274m 3. typical performance curves 3.2 startup and shutdown operating condition: t a = +25c, no air flow. c out = 1 x 470f poscap + 12 x 100f ceramic. typical values are us ed unless otherwise noted. figure 11. single channel startup 12v in , 1.5v out , 30a figure 12. single channel startup 12v in , 1.5v out , 0a figure 13. single channel shutdown 12v in , 1.5v out , 30a figure 14. single channel shutdown 12v in , 1.5v out , 0a sw (10v/div) i out (20a/div) v ou t (750mv/div) pg (5v/div) 2ms/div sw (10v/div) i out (20a/div) v out (750mv/div) pg (5v/div) 2ms/div sw (10v/div) i out (20a/div) v out (750mv/div) pg (5v/div) 100s/div sw (10v/div) i out (20a/div) v out (750mv/div) pg (5v/div) 1s/div
fn8931 rev.1.00 page 18 of 81 jan 4, 2018 isl8274m 3. typical performance curves 3.3 derating curves all of the following curves were plotted at t j = +125c. the derating curves were measured on the evaluation board. for test conditions, refer to table 2 on page 10 . load current is applied per channel, two channels are operati ng at the same time. figure 15. 12v in to 1v out figure 16. 5v in to 1v out figure 17. 12v in to 1v out figure 18. 5v in to 1v out figure 19. 12v in to 1.5v out figure 20. 5v in to 1.5v out 0 5 10 15 20 25 30 35 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 615khz 0 5 10 15 20 25 30 35 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 615khz 0 5 10 15 20 25 30 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 296khz 0 5 10 15 20 25 30 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 296khz 0 5 10 15 20 25 30 35 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 889khz 0 5 10 15 20 25 30 35 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 889khz
fn8931 rev.1.00 page 19 of 81 jan 4, 2018 isl8274m 3. typical performance curves figure 21. 12v in to 2.5v out figure 22. 5v in to 2.5v out figure 23. 12v in to 5v out all of the following curves were plotted at t j = +125c. the derating curves were measured on the evaluation board. for test conditions, refer to table 2 on page 10 . load current is applied per channel, two channels are operati ng at the same time. (continued) 0 5 10 15 20 25 30 35 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 1067khz 0 5 10 15 20 25 30 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 889khz 0 5 10 15 20 25 30 25 45 65 85 105 125 load current (a) ambient temperature ( o c) 0lfm 200lfm 400lfm f sw = 1067khz
fn8931 rev.1.00 page 20 of 81 jan 4, 2018 isl8274m 3. typical performance curves 3.4 transient response performance operating condition: t a = +25c, no air flow. refer to table 2 on page 10 for output capacitor and ascr se ttings. typical values are use d unless otherwise noted. figure 24. 0a-15a, >10a/s, 12v in ,1v out , 615khz figure 25. 0a-15a, >10a/s, 12v in ,1.5v out , 889khz figure 26. 0a-15a, >10a/s, 12v in ,1.8v out , 889khz figure 27. 0a-15a, >10a/s, 12v in , 2.5v out , 1067khz figure 28. 0a-12.5a, >10a/s, 12v in , 3.3v out , 800khz figure 29. 0a-12.5a, >10a/s, 12v in , 5v out , 1067khz i out (5a/div) v out (50mv/div) 50s/div i out (5a/div) v out (50mv/div) 50s/div i out (5a/div) v out (50mv/div) 50s/div i out (5a/div) v out (50mv/div) 50s/div i out (5a/div) v out (50mv/div) 50s/div i out (5a/div) v out (50mv/div) 50s/div
fn8931 rev.1.00 page 21 of 81 jan 4, 2018 isl8274m 4. functional description 4. functional description 4.1 smbus communications the isl8274m provides a pmbus digital interf ace that enables the user to conf igure all aspect s of the modul e operation as well as monitor the input and output parameters. t he isl8274m can be used with any smbus host device. in addition, the module is compatible with pmbus power system m anagement protocol specification parts i and ii version 1.2. the isl8274m accepts most standard pmbus comma nds. when confi guring the devi ce using pmbus commands, it is recommended that the enable pin is tied t o sgnd. the smbus device addre ss is the only parameter that must be set by the external pins. all other device parameters can be set using pmbus commands. the isl8274m can operate without the pmbus in pin-strap mode wi th configurations programmed by pin-strap resistors, such as output voltage , ascr setting, switching freq uency, ocp limit, devi ce smbus address, input uvlo, soft-start/stop, and tracking. 4.2 output voltage selection the output voltages of both channels may be set to a voltage be tween 0.6v and 5v if the input voltage is higher than the desired output voltage b y an amount sufficient to main tain regulation. the vset1/2 pins are used to set the output voltage vout1/2 to levels as shown in table 3 . the rset1/2 resistor is placed between the vset1/2 p ins and sgnd. a standard 1% resi stor is required. table 3. output voltage resistor settings vout1/2 (v) rset1/2 (k) 1low 1.5 open 3.3 high 0.6 10 0.675 11 0.7 12.1 0.72 13.3 0.75 14.7 0.8 16.2 0.85 17.8 0.9 19.6 0.93 21.5 0.95 23.7 0.98 26.1 1.03 28.7 1.05 31.6 1.1 34.8 1.12 38.3 1.15 42.2 1.2 46.4 1.25 51.1 1.3 56.2 1.35 61.9
fn8931 rev.1.00 page 22 of 81 jan 4, 2018 isl8274m 4. functional description the output voltage may also be s et to any value between 0.6v an d 5v using the pmbus command vout_command. this device supports dynamic voltage scaling by a llowing change to the output voltage set point during regulation. the vol tage transition rate is specifi ed by the pmbus command vout_transition_rate. by default, v out_max is set to 110% of v out set by the pin-strap resistor, w hich can be chan ged to any val ue up to 5.5v by the pmbus command vout_max. 4.3 soft-start, stop delay, and ramp times the isl8274m follows an internal start-up procedure after power is applied to the vdd pin. the module requires approximately 60ms to 70ms to ch eck for specific values stored in its internal memory and programmed by pin-strap resistors. once this process is completed, the device is ready to accept comman ds through the pmbus interface and the module is ready to be enabled. if the module is to be synchronized to an external clock source, the clock frequency must be stable before assertin g the en pin. it may be necessary to set a delay from when an enable signal i s received until the output voltage starts to ramp to its target value. in addition, t he designer may wish to precise ly set the time required for v out to ramp to its target value after the delay period has expired. these features can be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned o n. the isl8274m gives the system designer several options for precisely and independently controlling both the de lay and ramp time period s. the soft-start delay period begins when the en pin is asserted and ends when the del ay time expires. the soft-start delay a nd ramp-up time can b e programmed to cust om values using the pmbus commands ton_delay and ton_rise. when the delay time is s et to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft-st art ramp period is set to 0ms, the output ramps up as quickly as the output load cap acitance and loop settings allow. it is generally r ecommended to set the soft-start ramp to a value greater than 2ms to prevent inadvertent fault c onditions due to excessive inrush current. similar to the soft-start delay and ramp-up time, the delay and ramp down time for soft-stop/off can be programmed using the pmbus commands toff_delay and toff_fall. i n addition, the module can be configured as immediate off using the command on_off_config, so that the internal mosfets are turned off immediately after the delay time expires. the ss/track pin can b e used to program the soft-start/stop del ay time and ramp time to some typical values as well as enable/disable the tracking function shown in table 4 on page 23 . 1.4 68.1 1.65 75 1.8 82.5 1.85 90.9 2 100 2.4 110 2.5 121 2.8 133 3 147 3.6 162 5 178 table 3. output voltage resistor settings (continued) vout1/2 (v) rset1/2 (k)
fn8931 rev.1.00 page 23 of 81 jan 4, 2018 isl8274m 4. functional description table 4. soft-start/stop and tracking resistor settings ton_delay toff_delay (ms) ton_rise toff_fall (ms) tracking r (k) ch1 ch2 ch1 ch2 ch1 ch2 5 5 2 2 no no low 5525no no open 5 5 5 2 no no high 5555no no 10 5102 2no no 11 5 10 2 5 no no 12.1 5 10 5 2 no no 13.3 5 10 5 5 no no 14.7 10 5 2 2 no no 16.2 10 5 2 5 no no 17.8 10 5 5 2 no no 19.6 10 5 5 5 no no 21.5 20 5 2 2 no no 23.7 20 5 5 5 no no 26.1 5 20 2 2 no no 28.7 5 20 2 5 no no 31.6 5 20 5 2 no no 34.8 5 20 5 5 no no 38.3 5n/a2n/ano track 100%42.2 5 n/a 2 n/a no track 50% 46.4 5n/a5n/ano track 100%51.1 5 n/a 5 n/a no track 50% 56.2 10 n/a 2 n/a no track 100% 61.9 10 n/a 2 n/a no track 50% 68.1 10 n/a 5 n/a no track 100% 75 10 n/a 5 n/a no track 50% 82.5 n/a 5 n/a 2 track 100% no 90.9 n/a 5 n/a 2 track 50% no 100 n/a 5 n/a 5 track 100% no 110 n/a 5 n/a 5 track 50% no 121 n/a 10 n/a 2 track 100% no 133 n/a 10 n/a 2 track 50% no 147 n/a 10 n/a 5 track 100% no 162 n/a 10 n/a 5 track 50% no 178
fn8931 rev.1.00 page 24 of 81 jan 4, 2018 isl8274m 4. functional description 4.4 voltage tracking numerous high performance syst ems place stringent demands on th e order in which the power supply voltages are turned on. this is particularly true when power ing fpgas, asics , and other advanced p rocessor devices that require multiple supply voltages to power a single die. in most cases, the i/o interface op erates at a higher voltage than the core and ther efore, the core supply voltage must not e xceed the i/o supply voltage according to the manufacturers' s pecifications. the isl8274m integrates a tracki ng scheme that allows one of it s outputs (channel 1 or channel 2) to track a voltage that is applied to the v trkp and vtrkn pins with no ext ernal components required. the vtrkp and vtrkn pins are analog inputs that, when the tracking mode is en abled, configure the voltage applied to the vtrkp and vtrkn pins to act as a reference for the device's out put regulation. figure 30 illustrates the typical connec tion and the two tracking modes: ? coincident - this mode configures the isl 8274m to ramp its output voltage at the same rate as the voltage applied to the v trk pin until it reaches its desired output vol tage. the device that is tracking another output voltage (slave) must be set to its desired steady-state output voltage. ? ratio-metric - this mode configures the isl8274m to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrkp and vtrkn pins. the default settin g is 50%, but an external resistor string can be used to configure a different tracking ratio. th e device that i s tracking another output vol tage (slave) must be set to its desired steady- state output voltage. figure 30. tracking modes vo2 v out time coincident ratiometric vo1 vo2 q1 q2 l1 c 1 isl8274m vtrkp vo1 vo2 time vo1 v in v out vtrkn
fn8931 rev.1.00 page 25 of 81 jan 4, 2018 isl8274m 4. functional description the master isl8274m device in a t racking group is defined as th e device that has the highe st target output voltage within the group. this master de vice will control the ramp rate of all tracking devices and is not configured for tracking mode. the maximum tracking rise time is 1v/ms. the sla ve device must be enable d before the master. any device that is configured for tracking mode will ignore its ton_delay and ton_rise settings and its output will take on the turn-on/t urn-off characteristics of the reference voltage present at the vtrkp and vtrkn pins. tracking mode can be config ured by using the track_config command. the vout_command needs to be set the same as the target trackin g voltage when tracking is enabled. for example, the vout_command of the page1 (vout2 which enables the tracking) needs to set to 1v if tracking 100% is selected and a ramp of 1v is applied to vtrkp and vtrkn . the vout_command of page 1 (vout2 which enables t he tracking) needs to set to 1v if tracki ng 50% is selected and a ra mp of 2v is applied to vtrkp and vtrkn. in tracking mo de, the minimum voltage that can be tracked is ~200mv. 4.5 power-good the isl8274m provides a power-g ood (pg) signal that indicates the output voltage is within a s pecified tolerance of its target level and no fault condition exists. by default, the pg pin asserts if the ou tput is within 10% of the target voltage. this limit may b e changed using the pmbus comma nd power_good_on. a pg delay period is defined as the time from when all conditio ns within the isl8274m for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an ext ernal reset controller to control external digit al logic. a pg delay can be programmed us ing the pmbus command power_good_delay. 4.6 switching frequency and pll the devices switching frequency is set from 296khz to 1067khz using the pin-strap method (combined with the average ocp limit setting) as shown in table 5 , or by using the pmbus comm and frequency_switch. the isl8274m incorporates an interna l phase-locked loop (pll) to cl ock the internal circu itry. the pll can be driven by an external clock sour ce connected to th e sync pin. i t is recommended that w hen using an external clock, the same frequency should be set in the frequency_switch command. if the external clock is lost, the module will automatically switch to the internal clock. when us ing the internal oscillator, the sync pin can be configured as a clock source and as an external sync to other m odules. refer to sync_config (e9h) on page 67 for more information. table 5. switching frequency and ocp limit resistor setting sync/ocp ocp avg r (k) fsw (khz) ch1 (a) ch2 (a) low 296 35 35 open 889 35 35 high 1067 35 35 10 296 30 35 11 296 30 30 12.1 296 25 35 13.3 296 25 30 14.7 296 25 25 16.2 320 25 35 17.8 320 25 30 19.6 320 25 25 21.5 320 20 30 23.7 320 20 25 26.1 364 25 35
fn8931 rev.1.00 page 26 of 81 jan 4, 2018 isl8274m 4. functional description 28.7 364 25 30 31.6 364 20 30 34.8 421 30 35 38.3 421 30 30 42.2 471 25 35 46.4 471 25 30 51.1 471 20 35 56.2 571 25 35 61.9 571 25 30 68.1 571 20 35 75 571 20 30 82.5 615 35 35 90.9 615 35 30 100 615 30 30 110 615 25 35 121 615 25 30 133 615 25 25 147 727 35 35 162 800 30 35 178 800 30 30 table 5. switching frequency and ocp limit resistor setting (continued) sync/ocp ocp avg r (k) fsw (khz) ch1 (a) ch2 (a)
fn8931 rev.1.00 page 27 of 81 jan 4, 2018 isl8274m 4. functional description 4.7 output overcurrent protection the isl8274m is protect ed from damage if the output is shorted to ground or if an overl oad condition is imposed on the output. average output ove rcurrent fault threshold can b e programmed by the pmbus command iout_avg_oc_fault_limit while th e peak output ov ercurrent fault threshold can be programmed by the pmbus command iout_oc_fault_limi t. the default r esponse from an average overcurrent fault is an immediate shutdown without retry. a continuous retry can be ena bled using the pmbus command mfr_iout_oc_fault_response. a hard bound of 50a is applied to t he peak overcurrent limit. the average ocp limit can be set by the sync/ocp pin strap as w ell. refer to table 5 on page 25 for more information. 4.8 loop compensation the module loop response is progr ammable through the pmbus comm and ascr_config or by using the pin-strap method (ascr1/2 pins) according to table 6 . the isl8274m uses the chargemode control algorithm that responds to the output current changes within a single pwm switching cycle, achievi ng a smaller total output voltage variation with less out put capacitance than traditional pwm controllers. table 6. ascr resistor setting ascr gain ascr residual r (k) 350 110 low 525 90 open 475 80 high 100 90 10 100 100 11 120 90 12.1 120 100 13.3 140 90 14.7 140 100 16.2 140 110 17.8 150 90 19.6 150 100 21.5 160 70 23.7 160 90 26.1 175 80 28.7 175 90 31.6 200 90 34.8 200 100 38.3 200 110 42.2 225 80 46.4 225 90 51.1 250 80 56.2 250 100 61.9 275 90 68.1 275 100 75 300 70 82.5 300 90 90.9
fn8931 rev.1.00 page 28 of 81 jan 4, 2018 isl8274m 4. functional description 4.9 smbus module address selection each module must have its own u nique serial address to distingu ish between other devices on the bus. the module address is set by conn ecting a resistor bet ween pins sa/cfg and sgnd. the sa/cfg pin also defines the input undervoltage lockout limit. the input undervoltge lockout (uvlo ) prevents the isl8274m from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 4.18v and 16v by using the pmbus command v in_uv_fault_limit. table 7 lists the available module addresses. a fault response to an input unde rvoltage fault can be programm ed by the pmbus command vin_uv_fault_response. if the input undervoltage fault retry is enabled, the module will shut down immediately once the input voltage falls below v uvlo and then continuously checks the input voltage after a retry de lay time, which can be configured from 35ms to 280ms. if the input voltage rise s above the input undervoltage warning level, the module will restart. the input undervoltage warning is 1.05*v uvlo by default and can be programmed by the pmbus command vin_uv_warn_limit. 350 100 100 450 100 110 450 110 121 500 70 133 500 90 147 600 100 162 600 110 178 table 7. smbus address and uvlo resistor setting pmbus address uvlo (v) r (k) 26h 4.5 low 28h 4.5 open 19h 10.8 10 1ah 4.5 11 1bh 10.8 12.1 1ch 4.5 13.3 1dh 10.8 14.7 1eh 4.5 16.2 1fh 10.8 17.8 20h 4.5 19.6 21h 10.8 21.5 22h 4.5 23.7 23h 10.8 26.1 24h 4.5 28.7 25h 10.8 31.6 26h 4.5 34.8 27h 10.8 38.3 28h 4.5 42.2 29h 10.8 46.4 table 6. ascr resistor setting (continued) ascr gain ascr residual r (k)
fn8931 rev.1.00 page 29 of 81 jan 4, 2018 isl8274m 4. functional description 4.10 output overvoltage protection the isl8274m offers an internal output overvoltage protection c ircuit that can be used to protect sensitive load circuitry from being s ubjected to a voltage higher than its pre scribed limits. a hardware comparator compares the actual output voltage (seen at pi ns vsen1/2p, vsen1/2n) to a th reshold set to 15% higher than the target output voltage (default setting). the fa ult threshold can be programme d to a desired level b y the pmbus command vout_ov_fault_limit. if the vsen 1/2p, vsen1/2n voltage exceeds this threshold, the module will initiate an immediate shutdown without retry. continuous retry can be en abled using the pmbus command vout_ov_fault_response. the retry delay time can be configured from 35ms to 280ms. internal to the module, two 100 resistors are populated from v out to vsen1/2p and sgnd to vsen1/2n to protect the module from overvol tage conditions in case of open at the voltage sensing pin s and differential remote sense traces due to assembly error. as long as differential rem ote sense traces have low resistance, v out regulation accuracy is not compromised. 4.11 output prebias protection an output prebias condition exists when an externally applied v oltage is present on a power supplys output before the power supplys control ic is enabled. certain applications require that the converter not be allowed to sink current during start-up if a pre bias condition exists at the ou tput. the isl8274m provides prebias protection by sampling the output voltage before initiating an output ramp. if a prebias voltage lower than the target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage and both d rivers are enabled. the output voltage is then ramped to the final regulati on value at the preconfigured ramp rate. the actual time the output takes to ramp from the prebias volta ge to the target voltage varies, depending on the prebias voltage. however, the total time elapsed from when the delay period expires to whe n the output reaches its target value will match the preconfigured r amp time (see figure 31 on page 30 ). 2ah 4.5 51.1 2bh 10.8 56.2 2ch 4.5 61.9 2dh 10.8 68.1 2eh 4.5 75 2fh 10.8 82.5 30h 4.5 90.9 31h 10.8 100 32h 4.5 110 33h 10.8 121 table 7. smbus address and uvlo resistor setting (continued) pmbus address uvlo (v) r (k)
fn8931 rev.1.00 page 30 of 81 jan 4, 2018 isl8274m 4. functional description if a prebias voltage is higher th an the target voltage after th e preconfigured delay period has expired, the target voltage is set to matc h the existing prebias voltage. thus, bot h drivers are enab led with a pwm duty cycle that would ideally create the prebias voltage. once the preconfigured soft-start ramp period has expired, the pg pin is asserted (assumi ng the prebias voltage is not higher than the overvoltage limit). the pwm then adjusts it s duty cycle to match the original target voltage and the output ramps down to the preconfigured output voltage. if a prebias voltage is higher than the overvoltage limit, the device does not initiate a tu rn-on sequence and declares an overvoltage fault condition. t he device then responds based on the output overvolta ge fault response setting programmed by the pmbus command vout_ov_fault_response. 4.12 thermal overload protection the isl8274m includes a thermal sensor that continuously measur es the internal temperature of the module and shuts down the controller when t he temperature exceeds the pres et limit. the factory default temperature limit is set to +115c, and can be changed using the pmbus command ot_fault_ limit. note that the temperature reading from the pmbus command is the te mperature of the internal contr oller, which is lowe r than the junction temperature of the module. the default response from an over-temperature fault is an immed iate shutdown without retry. retry settings can be programmed using the pmbus comman d ot_fault_response. hysteresi s is implemented with the over-temperature fault retry. if a retry is enabled, the module will shut down immediately upon an over-temperature fault event and then continuously check the temperature after a retry delay time, which can be configured from 35ms to 280ms. if the temperatur e falls below th e over-temperat ure warning level, the m odule will restart. the over-temperature warning is +105 c by default a nd programmable using the pmbus command ot_warn_limit. figure 31. output responses to prebias voltages desired output voltage prebias voltage v out time ton- delay ton- rise desired output voltage prebias voltage v out time v prebias < v target v prebias > v target ton- rise ton- delay
fn8931 rev.1.00 page 31 of 81 jan 4, 2018 isl8274m 4. functional description 4.13 digital-dc bus the digital-dc communications (ddc) bus is used to communicate between the renesas dig ital power modules and digital controllers. the ddc bus provides the communication channel between devices for features such as current sharing, sequencing and fault spreading. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the dd c bus in order to guarantee the rise time as shown in (eq. 1) : where r pu is the ddc bus pull- up resistance and c load is the bus loading. the pull-up resistor may be tied to an external 3.3v or 5v supply as lo ng as this voltage is present b efore or during the device power-up. in principle, each device connected t o the ddc bus represents approximately 1 0pf of capacitive loading, and each inch of fr4 pcb trace introduces approximate ly 2pf. the ideal design uses a central pull-up resistor th at is well-matched to the total load capacitance. 4.14 phase spreading when multiple point-of-load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device, such that not all devices start to switc h simultaneously. setting e ach converter to start its switching cycle at a different point in time can dramatically r educe input capacitance requ irements and efficiency losses. because the peak current d rawn from the input supply is effectively spread out ove r a period of time, the peak current drawn at any given moment is reduced, and the powe r losses proportional to the i rms 2 are reduced dramatically. to enable phase spreading, all converters must be synchronized to the same switching clock. the phase offset of each device may also be set to any value bet ween 0 and 360 in 22.5 increments with the pmbus command interleave. the internal two phas es of the module always mainta in a phase difference of 180. 4.15 fault spreading digital-dc modules and devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group using the pmbus command ddc_group. when a nondestr uctive fault occurs, the device shuts down and broadcasts the fault event o ver the ddc bus. the other devi ces on the ddc bus shut down simultaneously, if configured to do so. note that fault retry is not supp orted in multiple modules with fault spreading enabled. 4.16 output sequencing a group of digital-dc modules or d evices can be configured to p ower up in a predeterm ined sequence. this feature is especially useful when powering advanced processors (fpgas and asics) that require one supply to reach its operating voltage befor e another supply reaching it i n order to avoid latch-up. multidevice sequencing can be achieved by confi guring each device with the pmbus command s equence. multiple device sequencing is configured by issuin g pmbus commands to as sign the preceding de vice in the sequencing chain as well as the device that follows the sequence. the enable pins of all devices i n a sequencing g roup must be ti ed together and driven high to initiate a sequenced turn-on of the group. the enable must be driven low to initiate a sequenced turnoff of the group. it is recommended to enable fault spreading with t he pmbus command ddc_group with in a sequencing group. rise time r pu c load 1 ? s ? ? = (eq. 1)
fn8931 rev.1.00 page 32 of 81 jan 4, 2018 isl8274m 4. functional description 4.17 monitoring using smbus the isl8274m can monitor a wide variety of different system par ameters using the pmbus commands: ? read_vin ? read_vout ? read_iout ? read_internal_temp ? read_duty_cycle ? read_freqeuncy ? read_vmon 4.18 snapshot parameter capture the isl8274m offers a special fea ture to capture parametric dat a and fault status follo wing a fault. a detailed description is provided in the pmbus commands description on page 42 under pmbus the commands snapshot and snapshot_control. 4.19 nonvolatile memory the isl8274m stores user configurations in internal nonvolatile memory. integrated securi ty measures ensure that the user can only restore the mo dule to a level that has been m ade available to them. during the initialization process, the isl8274m checks for stored values contained in its internal nonvolatile memory. modules are shipped with factory defaults configuration and mos t settings can be overwritten by pmbus commands and can be stored in non volatile memory by the pmbus c ommand store_user_all.
fn8931 rev.1.00 page 33 of 81 jan 4, 2018 isl8274m 5. layout guide 5. layout guide to achieve stable operation, low losses, and good thermal perfo rmance, some layout considerations are necessary ( figure 32 ). refer to the isl8274me val1z layout design. ? establish separate sgnd plane an d pgnd planes, then connect sg nd to pgnd plane on a middle layer and underneath pad6 with a single point connection. for sgnd and pg nd pin connections, such as small pins h16, j16, m5 and m17..., us e multiple vias for each pin to connect t o inner sgnd or pgnd layers. ? place enough ceramic capacitors between vin and pgnd, vout and pgnd and bypass cap acitors between vdd, vdrv and the ground plane, as close to the module as possible t o minimize high frequency noise. it is very critical to place the output ceramic capacit ors close to the vout pads and in the direction of the load current path in order to create a low impedance path for the high frequency inductor rip ple current. ? use large copper areas for power paths (vin, pgnd, vout) to mi nimize conduction loss and thermal stress. also, use multiple vias to connect the power planes in different laye rs. it is recommended to enlarge pad11 and pad9 to place more vias on them. the ceram ic capacitors cin can be plac ed on the bottom layer under these two pads. ? connect remote sensing traces t o the regulation point to achie ve a tight output voltage r egulation and place the two traces in parallel. route a trace fr om vsen1/2n and vsen1/2p to the point of load where the tight output voltage is desired. avoid routing any sens itive signal traces, such as the vsenn, vsenp sensing lines near the sw pins. ? pad14 and 16 (sw1 and sw2) are no isy pads, but they are benefi cial for thermal dissipati on. if the noise issue is critical for the appli cations, it is recommended to use only th e top layer for the sw p ads. for better thermal performance, use multiple vias on these pads to connect into th e sw inner and bottom laye rs. however, use caution when placing a limited area of sw planes in any layer. the sw p lanes should avoid the sensing signals and should be surrounded by the pgnd layer to avoid noise coupling. ? for pins swd1 (l3) and swd2 (p1 0), it is recommended to connec t to the related sw1 a nd sw2 pads with short loop traces. the tr ace width should be more than 20 mils. figure 32. recommended layout pgnd vin vin pgnd pgnd sgnd vsen1p vsen1n kelvin connections for both ch1 and ch2 cin cin pgnd cout1 cout2 vout1 vout2
fn8931 rev.1.00 page 34 of 81 jan 4, 2018 isl8274m 5. layout guide 5.1 thermal considerations experimental power loss curves along with ja from thermal modeling analysis can be used to evaluate the the rmal consideration for the module. the derating curves are derived f rom the maximum power allowed while maintaining the temperature below the maximum junction temperat ure of +125c. the derating curves are derived based on tests of the isl8274meval1z evaluation board, which is an 8-layer board 4.5x4inch in size with 2oz cu on the top and bottom layers, 1o z cu on the inner layers, and m ultiple via interconnects. i n the actual application, other heat sources and design m argins should be considered. 5.2 package description the structure of the isl8274m b elongs to the high density array (hda) no-lead package. this kind of package has advantages, such as good t hermal and electrical conductivit y, low weight, and small size. the hda package is applicable for surface mounting technology and is being more re adily used in the industry. the isl8274m contains several types of devices, includ ing resistors, capacitors, indu ctors, and control ics. t he isl8274m is a copper leadframe based packag e with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper leadframe and multicomp onent assembly is overmolded with a polymer mold compound to protect these devices. the package outline and typical p cb layout pattern design and t ypical stencil pattern design are shown on pages 73 through page 79 . the module has a small size of 18mmx 23mmx7.5mm. 5.3 pcb layout pattern design the bottom of isl8274m is a leadfr ame footprint, w hich is attac hed to the pcb by the sur face mounting process. the pcb layout pattern is shown on pages 77 through 79 . the pcb layout pattern is an array of solder mask defined pcb lands which align with the perimeters of the hda ex posed pads and i/o termination dimensions. the thermal lands on the pcb layout a lso feature an a rray of solder mask defined lands and sh ould match 1:1 with the package exposed die pads. 5.4 thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down a nd connects to buried copper plane(s), should be placed under the thermal land. the vias shou ld be about 0.3mm t o 0.33mm in diameter with the barrel plated to about 1.0 oz. of copper. although adding more vias (by decreasi ng via pitch) will improve the thermal performance, diminishing returns will be seen as the number of vias is increased . simply use as many vias as practical for the thermal land size and your board design rules will allow. all vias should be capped and filled to avoid scavenging solder from the i/o solder joints and creating voids. 5.5 stencil pattern design reflowed solder joints on the pe rimeter i/o lands should have a bout a 50m to 75m (2 mil to 3 mil) standoff height. the solder paste stencil design is the first step in de veloping optimized, reliable solder joins. stencil aperture size to sol der mask defined pcb land size ratio should typically be 1:1. the a perture width may be reduced slightly to help prevent solder bridging between adjace nt i/o lands. to reduce so lder paste volume on the larger thermal lands, it is reco mmended that an array of smalle r apertures be used instead of one large aperture. it is recommended that the stencil prin ting area cover 50% to 80% of the pcb layout pattern. a typical sol der stencil pattern is shown on pages 71 through 77 . the gap width between pads is 0 .6mm. the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezo idal walls is recomme nded. electropolish ing smooths the apertu re walls resulting in reduced surface friction and better paste release, which reduce s voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a brick like paste depo sit that assists in firm componen t placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) hda.
fn8931 rev.1.00 page 35 of 81 jan 4, 2018 isl8274m 5. layout guide 5.6 reflow parameters due to the low mount height of the hda, no-clean type 3 solde r paste per ansi/j-std-005 is recommended. a nitrogen purge is also recomme nded during reflow. a system bo ard reflow profile depen ds on the thermal mass of the entire populated board, so it is not pract ical to define a specific soldering prof ile just for the hda. the profile given in figure 33 is provided as a guideline, which can be customized for varyin g manufacturing practices and applications. figure 33. typical reflow profile 0 300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +150c to +200c for 60s~180s ramp rate ? 1.5c from +70c to +90c peak temperature ~+245c; typically 60s-150s above +217c keep less than 30s within 5c of peak temp.
fn8931 rev.1.00 page 36 of 81 jan 4, 2018 isl8274m 6. pmbus command summary 6. pmbus command summary command code command name description type data format default value default setting page 00h page selects controller 0, 1, or both. r/w byte bit 00h channel 1 page 42 01h operation sets enable, disable, and v out margin modes. r/w byte bit page 42 02h on_off_config configures the en pin and pmbus commands to turn the unit on/off. r/w byte bit 17h hardware pin enable, immediate off page 42 03h clear_faults clears fault indications. send byte page 43 15h store_user_all stores all pmbus values written since last restore at user level. send byte page 43 16h restore_user_all restores pmbus settings that were stored using store_user_all. send byte page 43 20h vout_mode preset to defined data format of v out commands. read byte bit 13h linear mode, exponent = -13 page 43 21h vout_command sets the nominal value of the output voltage. r/w word l16u pin-strap page 44 23h vout_cal_offset applies a fixed offset voltage to the vout_command. r/w word l16s 0000h 0v page 44 24h vout_max sets the maximum possible value of v out . 110% of pin-strap v out . r/w word l16u 1.1*v out pin-strap page 44 25h vout_margin_high sets the value of the v out during a margin high. r/w word l16u 1.05*v out pin-strap page 44 26h vout_margin_low sets the value of the v out during a margin low. r/w word l16u 0.95*v out pin-strap page 45 27h vout_transition_rate sets the transition rate during margin or other change of v out . r/w word l11 ba00h 1v/ms page 45 28h vout_droop sets the loadline (v/i slope) resistance for the rail. r/w word l11 0000h 0mv/a page 45 33h frequency_switch sets the switching frequency. r/w word l11 pin-strap page 45 37h interleave configures a phase offset between devices sharing a sync clock. r/w word bit 0021h(ch1) /0022(ch2) 180 phase shift between ch1/ch2 page 46 38h iout_cal_gain sense resistance for inductor dcr current sensing. r/w word l11 b2c3(ch1)/ b2d7(ch2) 0.69m (ch1)/ 0.7m (ch2) page 46 39h iout_cal_offset sets the current-sense offset. r/w word l11 b529(ch1)/ bddc(ch2) -0.71a(ch1)/ -1.07a(ch2) page 46
fn8931 rev.1.00 page 37 of 81 jan 4, 2018 isl8274m 6. pmbus command summary 40h vout_ov_fault_limit sets the v out overvoltage fault threshold. r/w word l16u 1.15*v out pin-strap page 46 41h vout_ov_fault_response configures the v out overvoltage fault response. r/w byte bit 80h disable and no retry page 47 42h vout_ov_warn_limit sets the v out overvoltage warn threshold. r/w word l16u 1.10*v out pin-strap page 47 43h vout_uv_warn_limit sets the v out undervoltage warn threshold. r/w word l16u 0.9*v out pin-strap page 47 44h vout_uv_fault_limit sets the v out undervoltage fault threshold. r/w word l16u 0.85*v out pin-strap page 48 45h vout_uv_fault_response configures the v out undervoltage fault response. r/w byte bit 80h disable and no retry page 48 46h iout_oc_fault_limit sets the i out peak overcurrent fault threshold. r/w word l11 e320h 50a page 48 4ah iout_oc_warn_limit sets the i out average overcurrent warning threshold. r/w word l11 0.9*iout_avg_oc _fault_limit page 49 4bh iout_uc_fault_limit sets the i out valley undercurrent fault threshold. r/w word l11 e4e0h -50a page 49 4fh ot_fault_limit sets the over-temperature fault threshold. r/w word l11 eb98h +115c page 49 50h ot_fault_response configures the over-temperature fault response. r/w byte bit 80h disable and no retry page 50 51h ot_warn_limit sets the over-temperature warning limit. r/w word l11 eb48h +105c page 50 52h ut_warn_limit sets the under-temperature warning limit. r/w word l11 dc40h -30c page 50 53h ut_fault_limit sets the under-temperature fault threshold. r/w word l11 e530h -45c page 51 54h ut_fault_response configures the under-temperature fault response. r/w byte bit 80h disable and no retry page 51 55h vin_ov_fault_limit sets the v in overvoltage fault threshold. r/w word l11 d3a0 14.5v page 51 56h vin_ov_fault_response configures the v in overvoltage fault response. r/w byte bit 80h disable and no retry page 52 57h vin_ov_warn_limit sets the input overvoltage warning limit. r/w word l11 d353h 13.3v page 52 58h vin_uv_warn_limit sets the input undervoltage warning limit. r/w word l11 1.03*v in uv fault limit page 52 command code command name description type data format default value default setting page
fn8931 rev.1.00 page 38 of 81 jan 4, 2018 isl8274m 6. pmbus command summary 59h vin_uv_fault_limit sets the v in undervoltage fault threshold. r/w word l11 pin-strap page 53 5ah vin_uv_fault_response configures the v in undervoltage fault response. r/w byte bit 80h disable and no retry page 53 5eh power_good_on sets the voltage threshold for power-good indication. r/w word l16u 0.9*v out pin-strap page 53 60h ton_delay sets the delay time from enable to start of v out rise. r/w word l11 pin-strap page 54 61h ton_rise sets the rise time of v out after enable and ton_delay. r/w word l11 pin-strap page 54 64h toff_delay sets the delay time from disable to start of v out fall. r/w word l11 pin-strap page 54 65h toff_fall sets the fall time for v out after disable and toff_delay. r/w word l11 pin-strap page 54 78h status_byte returns an abbreviated status for fast reads. read byte bit 00h no faults page 55 79h status_word returns information with a summary of the units's fault condition. read word bit 0000h no faults page 56 7ah status_vout returns the v out specific status. read byte bit 00h no faults page 56 7bh status_iout returns the i out specific status. read byte bit 00h no faults page 57 7ch status_input returns specific status specific to the input. read byte bit 00h no faults page 57 7dh status_temp returns the temperature specific status. read byte bit 00h no faults page 57 7eh status_cml returns the communication, logic and memory specific status. read byte bit 00h no faults page 58 80h status_mfr_specific returns the vmon and external sync clock specific status. read byte bit 00h no faults page 58 88h read_vin returns the input voltage reading. read word l11 page 58 8bh read_vout returns the output voltage reading. read word l16u page 59 8ch read_iout returns the output current reading. read word l11 page 59 8dh read_internal_temp returns the temperature reading internal to the device. read word l11 page 59 94h read_duty_cycle returns the duty cycle reading during the enable state. read word l11 page 59 command code command name description type data format default value default setting page
fn8931 rev.1.00 page 39 of 81 jan 4, 2018 isl8274m 6. pmbus command summary 95h read_frequency returns the measured operating switch frequency. read word l11 page 59 99h mfr_id sets a user defined identification. r/w block asc null page 60 9ah mfr_model sets a user defined model. r/w block asc null page 60 9bh mfr_revision sets a user defined revision. r/w block asc null page 60 9ch mfr_location sets a user defined location identifier. r/w block asc null page 60 9dh mfr_date sets a user defined date. r/w block asc null page 61 9eh mfr_serial sets a user defined serialized identifier. r/w block asc null page 61 a8h legacy_fault_group sets rail ids of legacy devices for fault spreading r/w block bit 00000000h no rail id specified page 61 b0h user_data_00 sets a user defined data. r/w block asc null page 62 d0h isense_config configures isense related features. r/w byte bit 06h 256ns blanking time, high range page 62 d1h user_config configures several user-level features. r/w byte bit 84h minimum duty control, pg open drain page 63 d3h ddc_config configures the ddc bus. r/w word bit pin-strap (rail id set based on pmbus address. phase id = 0; phases in rail = 1 page 63 d4h power_good_delay sets the delay between v out > pg threshold and asserting the pg pin. r/w word l11 c300h 3ms page 64 dfh ascr_config configures ascr control loop. r/w block cus pin-strap page 64 e0h sequence identifies the rail ddc id to perform multi-rail sequencing. r/w word bit 0000h prequel and sequel disabled page 65 e1h track_config configures voltage tracking modes r/w byte bit pin-strap setting page 66 e2h ddc_group sets rail ddc ids to obey faults and margining spreading information. r/w block bit ignore broadcast vout_command, operation page 66 e4h device_id returns the 16-byte (character) device identifier string. read block asc reads device version page 67 e5h mfr_iout_oc_fault_ response configures the i out overcurrent fault response. r/w byte bit 80h disable and no retry page 67 e6h mfr_iout_uc_fault_ response configures the i out undercurrent fault response. r/w byte bit 80h disable and no retry page 67 e7h iout_avg_oc_fault_limit sets the i out average overcurrent fault threshold. r/w l11 set by sync/ocp pin-strap page 68 command code command name description type data format default value default setting page
fn8931 rev.1.00 page 40 of 81 jan 4, 2018 isl8274m 6. pmbus command summary e8h iout_avg_uc_fault_limit sets the i out average undercurrent fault threshold. r/w l11 dc40h -30a page 68 e9h sync_config configures the sync pin. r/w byte bit 00h pin-strap (set based on sync/ocp) page 69 eah snapshot returns 32-byte read-back of parametric and status values. read block bit page 69 ebh blank_params returns recently changed parameter values. read block bit ff...ffh page 70 f3h snapshot_control snapshot feature control command. r/w byte bit page 70 f4h restore_factory restores device to the factory default values. send byte page 70 f5h mfr_vmon_ov_fault_limit returns the vmon overvoltage threshold. read word l11 cb00h 6v page 70 f6h mfr_vmon_uv_fault_limit returns the vmon undervoltage threshold. read word l11 ca00h 4v page 71 f7h mfr_read_vmon returns the vmon voltage reading. read word l11 page 71 f8h vmon_ov_fault_response returns the vmon overvoltage response. read byte bit 80h disable and no retry page 71 f9h vmon_uv_fault_response returns the vmon undervoltage response. read byte bit 80h disable and no retry page 71 command code command name description type data format default value default setting page
fn8931 rev.1.00 page 41 of 81 jan 4, 2018 isl8274m 6. pmbus command summary 6.1 pmbus data formats linear-11 (l11) l11 data format uses 5-bit twos complement exponent (n) and 11 -bit twos complement mantissa (y) to represent real world decimal value (x). relation between real world decima l value (x), n, and y is: x = y2 n linear-16 unsigned (l16u) l16u data format uses a fixed e xponent (hard-coded to n = -13h) and a 16-bit unsigned integer mantissa (y) to represent real world decimal valu e (x). relation between real w orld decimal value (x), n and y is: x = y2 -13 linear-16 signed (l16s) l16s data format uses a fixed exponent (hard-coded to n = -13h) and a 16-bit twos complement mantissa (y) to represent real world decimal value (x). relation between real world decima l value (x), n and y is: x = y2 -13 bit field (bit) an explanation of the bit field for each command is provided in pmbus commands description on page 41 . custom (cus) an explanation of the custom da ta format for each command is pr ovided in pmbus commands description on page 41 . a combination of bit field and integer is a common type of cu stom data format. ascii (asc) a variable length string of text characters uses ascii data for mat. 6.2 pmbus use guidelines the pmbus is a powerful tool that allows the user to optimize c ircuit performance by configuring devices for their application. when configuring a device in a circuit, the device should be disabled whenever most settings are changed with pmbus commands. some exceptions to this recommenda tion are operation, on_off_config, clear_faults, vout_command, vout_margin_high, vout_margin_low, and asccr_config. while the device i s enabled any command can be re ad. many commands do not take effect until after the device has been re-en abled, hence the recommendation that commands that cha nge device settings are written while the device is disabled. when sending the store_user_all and restore_user_all commands, it is recommended that no other commands are sent to the device for 100ms after sending store o r restore commands. in addition, there should be a 2ms delay between repeated read commands sent to the same device. when sending any other command, a 5ms delay is recomm ended between r epeated commands sent to the same device. 6.3 summary all commands can b e read at any time. always disable the dev ice when writing comm ands that change dev ice settings. excepti ons to this rule are commands intended to be written while the device is enabled, fo r example, vou t_margin_high. to be sure a change to a device setting has taken effect, write the store_user_all command, then cycle input power and re-enable. data byte high data byte low exponent (n) mantissa (y) 76543210 76543210
fn8931 rev.1.00 page 42 of 81 jan 4, 2018 isl8274m 7. pmbus commands description 7. pmbus commands description page(00h) definition: select channel 1, cha nnel 2 or both channe ls to receive comman ds. all commands following this command will be receive d and acted on by the selected channel o r channels. data length in bytes: 1 data format: bit type : r/w default value: 00h (page 0) units: n/a operation (01h) definition: sets enable, disable and v out margin settings. data length in bytes : 1 data forma t: bit type : r/w default value : units : n/a on_off_config (02h) definition: configures the interpretation a nd coordination of the operatio n command and the enable pin (en). data length in bytes : 1 data format : bit type : r/w default value : 17h (device starts from enable pin with soft-off) units : n/a bits 7:4 bits 3:0 page 0000 0000 0 0000 0001 1 1111 1111 both settings actions 00h immediate off (no sequencing) 40h soft off (with sequencing) 80h on - nominal 90h on - margin low a0h on - margin high settings actions 16h device starts from enable pin with soft off. 17h device starts from enable pin with immediate off. 1ah device starts from operation command with soft off. 1bh device starts from operation command with immediate off.
fn8931 rev.1.00 page 43 of 81 jan 4, 2018 isl8274m 7. pmbus commands description clear_faults (03h) definition : clears all fault bits in all re gisters and releases the salrt pin (if asserted) simu ltaneously. if a fault condition still exists, the bit will reassert immediately. this command will not restart a device if it has shut down, it will only clear the faults. data length in bytes : 0 byte data format : n/a type : send byte default valu e: n/a units : n/a reference: n/a store_user_all (15h) definition : stores all pmbus settings from the operating memory to the nonvolatile user store memory. to clear the user store, perform a restore_fac tory then store_user_all. to a dd to the user store, perform a restore_user_all, write commands to be added, then store_user_a ll. this command can be used during device operation, but the device will be unresponsive for 20ms while storing values. data length in bytes : 0 data format : n/a type : send byte default value : n/a units: n/a restore_user_all (16h) definition: restores all pmbus settings from the user store memory to the operating memory. command performed at power-up. security level is ch anged to level 1 following thi s command. this command can be used during device operation, but the device will be unresponsive for 20ms while s toring values. data length in bytes: 0 data format: n/a type: send byte default value: n/a units: n/a vout_mode (20h) definition: reports the v out mode and provides the exponent used in calculating several v out settings. fixed with linear mode with default exponent (n) = -13 data length in bytes: 1 data format: bit type: read only default value: 13h (linear mode, n = -13) units: n/a
fn8931 rev.1.00 page 44 of 81 jan 4, 2018 isl8274m 7. pmbus commands description vout_command (21h) definition: sets or reports the target output voltage. this command cannot set a value higher than vout_max. data length in bytes: 2 data format: l16u type: r/w default value: pin-strap setting units: volts range: 0v to vout_max vout_cal_offset (23h) definition: applies a fixed offset voltage to the output voltage command v alue. this command is typically used by the user to calibrate a device in the application circuit. data length in bytes: 2 data format: l16s type: r/w default value: 0000h units: volts vout_max (24h) definition: sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. the intent of this command is to provide a safegu ard against a user accide ntally setting the output voltage to a possibly destructive level rather than to be the p rimary output overprotecti on. default value can be changed using pmbus. data length in bytes: 2 data format: l16u type: r/w default value: 1.10xvout_command pin-strap setting units: volts range: 0v to 5.5v vout_margin_high (25h) definition: sets the value of the v out during a margin high. this vout _margin_high command loads the unit with the voltage to which the output is to be changed when the operation command is set to margin high. data length in bytes: 2 data format: l16u type: r/w default value: 1.05 x vout_command pin-strap setting units: v range: 0v to vout_max
fn8931 rev.1.00 page 45 of 81 jan 4, 2018 isl8274m 7. pmbus commands description vout_margin_low (26h) definition: sets the value of the v out during a margin low. this vout_margin_low command loads the uni t with the voltage to which the output is to be changed when the operation command is set to margin low. data length in bytes: 2 data format: l16u type: r/w default value: 0.95 x vout_command pin-strap setting units: v range: 0v to vout_max vout_transition_rate (27h) definition: sets the rate at which the output should change voltage when t he device receives the vout_command or an operation command (margin high, margin low) that causes t he output voltage to change. the maximum possible positive value of the two data bytes indicates that th e device should make the transition as quickly as possible. data length in bytes: 2 data format: l11 type: r/w default value: ba00h (1v/ms) units : v/ms range: 0.1v/ms to 4v/ms vout_droop (28h) definition: sets the effective load line (v /i slope) for the rail in which the device is used. it is the rate, in mv/a, at which the output voltage decreases (or increases) with increasi ng (or decreasing) output current for use with adaptive voltage positioning schemes or mul ti-module curren t sharing. in current sharing configurat ion, vout_droop set in each module stands for the d roop seen by the load. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: mv/a range: 0mv/a to 40mv/a frequency_switch (33h) definition: sets the switching frequency of the device. initial default val ue is defined by a pin-strap and this value can be overridden by writing this command through the pmbus. if an external sync is utilized, this value should be set as close as possible to the externa l clock value. the output must be disabled when writing this command. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: khz range: 296khz to 1066khz
fn8931 rev.1.00 page 46 of 81 jan 4, 2018 isl8274m 7. pmbus commands description interleave (37h) definition: configures the phase offset of a device that is sharing a commo n sync clock with o ther devices. the phase offset of each device can be set to any value between 0 and 360 in 22.5 increments. the internal two phases of the module always maintain a phase difference of 180. data length in bytes: 2 data format: bit type: r/w default value: 0021h (page0), 0022h (page1) units: n/a iout_cal_gain (38h) definition: sets the effective impedance acros s the current sense circuit f or use in calculating output current at +25c. data length in bytes: 2 data format: l11 type : r/w default value: ch1: b2c3(0.69m); ch2: b2d7(0.7m) units: m iout_cal_offset (39h) definition: nulls out any offsets in the ou tput current sensing circuit fo r each phase, and comp ensates for delayed measurements of curr ent ramp due to i sense blanking time. data length in bytes: 2 data format: l11 type : r/w default value: ch1: b529(-0.71a); ch2: bddc(-1.07a) units: a vout_ov_fault_limit (40h) definition: sets the v out overvoltage fault threshold. data length in bytes: 2 data format: l16u type: r/w default value: 1.15xvout_command pin-strap setting units: v range: 0v to vout_max bits purpose value description 15:4 reserved 0 reserved 3:0 position in group 0 to 15 set s position of the device's rail w ithin the group.
fn8931 rev.1.00 page 47 of 81 jan 4, 2018 isl8274m 7. pmbus commands description vout_ov_fault_response (41h) definition: configures the v out overvoltage fault response. note that the device cannot be set to ignore this fault mode. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units : n/a vout_ov_warn_limit (42h) definition: sets the v out overvoltage warning threshold. the power-good signal is pulled low when the output voltage goes higher than this threshold. data length in bytes : 2 data format: l16u type: r/w default value: 1.10xvout_command pin-strap setting units: v range: 0v to vout_max vout_uv_warn_limit (43h) definition: sets the v out undervoltage warning threshold. the power-good signal is pulled low when the output voltage goes lower than this threshold. data length in bytes: 2 data format: l16u type: r/w default value: 0.90 x vout_command pin-strap setting units: v range: 0v to vout_max bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1) * 35ms. set s the time between retries in 35ms
fn8931 rev.1.00 page 48 of 81 jan 4, 2018 isl8274m 7. pmbus commands description vout_uv_fault_limit (44h) definition: sets the v out undervoltage fault threshold. thi s fault is masked during ramp or when disabled. data length in bytes: 2 data format: l16u type: r/w default value: 0.85 x vout_command pin-strap setting units: v range: 0v to vout_max vout_uv_fault_response (45h) definition: configures the v out undervoltage fault response. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, no retry) units: n/a iout_oc_fault_limit (46h) definition: sets the i out peak overcurrent fault threshold. this limit is applied to cur rent measurement samples taken after the current sense blanking time has expired. a fault occu rs after this limit is exceed ed. the recommended peak ocp limit is determined by (eq. 2) . a hard bound of 50a is applied to the command value. this featu re shares the oc fau lt bit operation (in status_iout) and oc fault respons e with the iout_avg_oc_fault_l imit. data length in bytes: 2 data format: l11 type: r/w default value: e320h (50a) units: a range: -100a to 100a bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1) * 35ms. set s the time between retries in 35ms increments. range is 35ms to 280ms. iout_oc_fault_limit iout_avg_oc_fault_limit 0.5 iripple pp C ? + ?? 130% ? = (eq. 2)
fn8931 rev.1.00 page 49 of 81 jan 4, 2018 isl8274m 7. pmbus commands description iout_oc_warn_limit (4ah) definition: sets the i out average overcurrent warning threshold. data length in bytes: 2 data format: l11 type: r/w default value: iout_avg_oc_fault_limit x 0.9 units: a range: -100a to 100a iout_uc_fault_limit (4bh) definition: sets the i out valley undercurrent fault thres hold. this limit is applied to current measurement samples taken after the current sense blanking time has expired. a faul t occurs after this limit is exceeded. the recommended valley ucp limit is determined by (eq. 3) : a hard bound of -50a is applied to the command va lue. this feat ure shares the uc fault bit operation (in status_iout) and uc fault response with iout_avg_uc_fault_limit . data length in bytes: 2 data format: l11 type: r/w default value: e4e0 (-50a) units: a range: -100a to 100a ot_fault_limit (4fh) definition: sets the temperature at which th e device should indicate an ove r-temperature faul t. note that the temperature must drop below ot_w arn_limit to clear this fault. data length in bytes: 2 data format: l11 type: r/w default value: eb98 (+115c) units: c range: 0c to +175c iout_uc_fault_limit iout_avg_uc_fault_limit 0.5 iripple pp C ? C ?? 130% ? = (eq. 3)
fn8931 rev.1.00 page 50 of 81 jan 4, 2018 isl8274m 7. pmbus commands description ot_fault_response (50h) definition: instructs the device on what action to take in response to an o ver-temperature fault. data length in bytes: 1 data format: bit type : r/w fault value: 80h (disable and no retry) units: n/a ot_warn_limit (51h) definition: sets the temperature at which th e device should indicate an ove r-temperature warning alarm. in response to the ot_warn_limit being exceed ed, the device sets the temper ature bit in status_word, sets the ot_warning bit in status_temperature, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: eb48h (+105c) units: c range : 0c to +175c ut_warn_limit (52h) definition: sets the temperature at which the device should indicate an und er-temperature warning alarm. in response to the ut_warn_limit being exceed ed, the device sets the temper ature bit in status_word, sets the ut_warning bit in status_temperature, and notifies the host. data length in bytes: 2 data format: l11 type : r/w default value: dc40h (-30c) units: c range : -55c to +25c bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
fn8931 rev.1.00 page 51 of 81 jan 4, 2018 isl8274m 7. pmbus commands description ut_fault_limit (53h) definition: sets the temperature, in degrees celsius, of the unit where it should indicate an under-temperature fault. note that the temperat ure must rise above u t_warn_limit to clea r this fault. data length in bytes: 2 data format: l11 type: r/w default value: e530h (-45c) units: c range: -55c to +25c ut_fault_response (54h) definition: configures the under-temperatur e fault response as defined by the following table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, no retry) units: n/a vin_ov_fault_limit (55h) definition: sets the v in overvoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w default value: d3a0 (14.5v) units: v range: 0v to 16v bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1) * 35ms. set s the time between retries in 35ms increments. range is 35ms to 280ms.
fn8931 rev.1.00 page 52 of 81 jan 4, 2018 isl8274m 7. pmbus commands description vin_ov_fault_response (56h) definition: configures the v in overvoltage fault response as def ined by the following table. t he delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a vin_ov_warn_limit (57h) definition: sets the v in overvoltage warning threshold. in response to the ov_warn_limi t being exceeded, the device sets the none of the above and input bits in status_word , sets the vin_ov_warning bit in status_input, and notifies the host. data length in bytes: 2 data format: l11 type : r/w protectable: yes default value: d353h (13.3v) units: v range : 0v to 16v vin_uv_warn_limit (58h) definition: sets the v in undervoltage warning threshold. if a vin_uv_fault occurs, the input voltage must rise above vin_uv_warn_limit to clear the fault, which provides hyst eresis to the fault thresh old. in response to the uv_warn_limit be ing exceeded, the device sets the none of the a bove and input bits in status_word, sets the vin_uv_war ning bit in status_input, and n otifies the host. data length in bytes: 2 data format: l11 type : r/w default value: 1.03 x vin_uv_fault_limit pin-strap setting units: v range : 0v to 12v bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1) * 35ms. set s the time between retries in 35ms increments. range is 35ms to 280ms.
fn8931 rev.1.00 page 53 of 81 jan 4, 2018 isl8274m 7. pmbus commands description vin_uv_fault_limit (59h) definition: sets the v in undervoltage fault threshold. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: v range: 0v to 12v vin_uv_fault_response (5ah) definition: configures the v in undervoltage fault response as de fined by the following table. the delay time is the time between restart attempts. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a power_good_on (5eh) definition: sets the voltage threshold for power-good indication. power-go od asserts with a d elay specified in power_good_delay after the outpu t voltage exceeds power_good_on and deasserts when the output voltage is less than vout_uv_warn _limit. it is r ecommended to s et power_good_on higher than vout_uv_fault_limit. data length in bytes: 2 data format: l16u type: r/w default value: 0.9xvout_command pin-strap setting units: v bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
fn8931 rev.1.00 page 54 of 81 jan 4, 2018 isl8274m 7. pmbus commands description ton_delay (60h) definition: sets the delay time from when t he device is ena bled to the sta rt of v out rise. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: ms range: 2ms to 256ms ton_rise (61h) definition: sets the rise time of v out after enable and ton_delay. in multi-module current sharing configuration where ascr is disab led for start up, the rise tim e of v out can be approximatel y calculated by (eq. 1) . data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: ms range: 0ms to 100ms toff_delay (64h) definition: sets the delay time from disable to start of v out fall. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: ms range: 0ms to 256ms toff_fall (65h) definition: sets the soft-off fall time for v out after disable and toff_delay. data length in bytes: 2 data format: l11 type: r/w default value: pin-strap setting units: ms range: 0ms to 100ms
fn8931 rev.1.00 page 55 of 81 jan 4, 2018 isl8274m 7. pmbus commands description status_byte (78h) definition: returns one byte of information with a summary of the most crit ical faults. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a bit number status bit name meaning 7 busy a fault was declared because the device was busy and unabl e to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, inc luding simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory, o r logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred.
fn8931 rev.1.00 page 56 of 81 jan 4, 2018 isl8274m 7. pmbus commands description status_word (79h) definition: returns two bytes of information with a summary of the unit's fault condition. based on the information in these bytes, the host can get mor e information by reading the a ppropriate status register s. the low byte of the status_word is the same register as the status_b yte (78h) comma nd. data length in bytes: 2 data format: bit type: read only default value: 0000h units: n/a status_vout (7ah) definition: returns one data byte with the status of the output voltage. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a bit number status bit name meaning 15 vout an output voltage fault or warning has occurred. 14 iout/pout an output current or output power fault or warning h as occurred. 13 input an input voltage, input current, or input power fault or warning has occurred. 12 mfg_specific a manufacturer s pecific fault or warning has occu rred. 11 power_good# the power_goo d signal, if present, is negated. 10 fans a fan or airflow fault or warning has occurred. 9 other a bit in status_other is set. 8 unknown a fault type not given in bits 15:1 of the status_word has been detected. 7 busy a fault was declared because the device was busy and unabl e to respond. 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, inc luding simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory, o r logic fault has occurred. 0 none of the above a fault or warning not listed in bits 7:1 has occurred. bit number status bit name meaning 7 vout_ov_fault indicates an output overvoltage fault. 6 vout_ov_warning indicates an output overvoltage warning. 5 vout_uv_warning indicates an output undervoltage warning. 4 vout_uv_fault indicates an output undervoltage fault. 3:0 n/a these bits are not used.
fn8931 rev.1.00 page 57 of 81 jan 4, 2018 isl8274m 7. pmbus commands description status_iout (7bh) definition: returns one data byte with the status of the output current. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a status_input (7ch) definition: returns the input voltage and inpu t current status information. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a status_temp (7dh) definition: returns one byte of information with a summary of any temperat ure related faults or warnings. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a bit number status bit name meaning 7 iout_oc_fault an output overcurrent fault has occurred. 6 iout_oc_lv_fault an output overcurrent and low voltage fault ha s occurred. 5 iout_oc_warning an output overcurrent warning has occurred. 4 iout_uc_fault an output undercurrent fault has occurred. 3:0 n/a these bits are not used. bit number status bit name meaning 7 vin_ov_fault an input overvoltage fault has occurred. 6 vin_ov_warning an input overvoltage warning has occurred. 5 vin_uv_warning an input undervoltage warning has occurred. 4 vin_uv_fault an input undervoltage fault has occurred. 3:0 n/a these bits are not used. bit number status bit name meaning 7 ot_fault an over-temperature fault has occurred. 6 ot_warning an over-temperature warning has occurred. 5 ut_warning an under-temperature warning has occurred. 4 ut_fault an under-temperature fault has occurred. 3:0 n/a these bits are not used.
fn8931 rev.1.00 page 58 of 81 jan 4, 2018 isl8274m 7. pmbus commands description status_cml (7eh) definition: returns one byte of information with a summary of any communic ations, logic, and/or memory errors. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a status_mfr_specific (80h) definition: returns one byte of information p roviding the status of the dev ice's voltage monitoring and clock synchronization faults. vmon ov/ uv warnings are set at 10% of the vmon_fault commands. data length in bytes: 1 data format: bit type: read only default value: 00h units: n/a read_vin (88h) definition: returns the input voltage reading. data length in bytes: 2 data format: l11 type: read only units: v bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 packet error was detected in the pmbus command. 4:2 not used 1 a pmbus command tried to write to a read-only or protected com mand, or a communication fault other than the ones listed in this table has occurred. 0 not used bit number field name meaning 7:6 reserved 5 vmon uv warning the voltage on the vmon pin has dropped 10% bel ow the level set by vmon_uv_fault_limit. 4 vmon ov warning the voltage on the vmon pin has risen 10% above the level set by vmon_ov_fault_limit. 3 external switching period fault loss of external clock synchro nization has occurred. 2 reserved 1 vmon uv fault the voltage on the vmon pin has dropped below the level set by vmon_uv_fault_limit. 0 vmon ov fault the voltage on the vmon pin has risen above the l evel set by vmon_ov_fault_limit.
fn8931 rev.1.00 page 59 of 81 jan 4, 2018 isl8274m 7. pmbus commands description read_vout (8bh) definition: returns the output voltage reading. data length in bytes: 2 data format: l16u type: read only units: v read_iout (8ch) definition: returns the output current reading. data length in bytes: 2 data format: l11 type: read only default value: n/a units: a read_internal_temp (8dh) definition: returns the controller junction temperature read ing from the i nternal temperature sensor. data length in bytes: 2 data format: l11 type: read only units: c read_duty_cycle (94h) definition: reports the actual duty cycle of the converter dur ing the enabl e state. data length in bytes: 2 data format: l11 type: read only units: % read_frequency (95h) definition: reports the actual switching fre quency of the converter during the enable state. data length in bytes: 2 data format: l11 type: read only units: khz
fn8931 rev.1.00 page 60 of 81 jan 4, 2018 isl8274m 7. pmbus commands description mfr_id (99h) definition: sets user defined ide ntification. the sum total of characters in mfr_id, mfr_model, mfr_revision, mfr_loca tion, mfr_date, mfr_serial, and user_data _00 plus one byte per command cannot exceed 128 character s. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, write thi s command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_model (9ah) definition: sets a user defined model. the s um total of characters in mfr_ id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one b yte per command cannot exceed 128 characters. this limitation includes multiple writes of thi s command before a store command. to clear multiple writes, perform a restore, write this command then perform a st ore/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_revision (9bh) definition: sets a user defined revision. th e sum total of c haracters in mf r_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one b yte per command cannot exceed 128 characters. this limitation includes multiple writes of thi s command before a store command. to clear multiple writes, perform a restore, write this command then perform a st ore/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a mfr_location (9ch) definition: sets a user defined l ocation identifier. the sum total of char acters in mfr_id, mfr_model, mfr_revision, mfr_loca tion, mfr_date, mfr_serial, and user_data _00 plus one byte per command cannot exceed 128 character s. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, write thi s command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a
fn8931 rev.1.00 page 61 of 81 jan 4, 2018 isl8274m 7. pmbus commands description mfr_date (9dh) definition: sets a user defined date. the s um total of characters in mfr_i d, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one b yte per command cannot exceed 128 characters. this limitation includes multiple writes of thi s command before a store command. to clear multiple writes, perform a restore, write this command then perform a st ore/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a reference: n/a mfr_serial (9eh) definition: sets a user defined s erialized identifier. the sum total of ch aracters in mfr_id, mfr_model, mfr_revision, mfr_loca tion, mfr_date, mfr_serial, and user_data _00 plus one byte per command cannot exceed 128 character s. this limitation includes multiple writes of this command before a store command. to clear multiple writes, perform a restore, write thi s command then perform a store/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a legacy_fault_group (a8h) definition: sets which rail ddc ids should be listened to for fault spread ing with legacy devices . the data sent is a 4-byte, 32-bit, bit vector where every bit represents a rails ddc id. a bit se t to 1 indicates a device ddc id to which the configured device will respond upon receiving a fault spreading event. in this vector, bit 0 o f byte 0 corresponds to the rail with ddc id 0. fol lowing through, bit 7 of byte 3 corresponds to the rail with ddc id 31. data length in bytes : 4 data format: bit type: block r/w default value: 00000000h (no rail id specified)
fn8931 rev.1.00 page 62 of 81 jan 4, 2018 isl8274m 7. pmbus commands description user_data_00 (b0h) definition: sets user defined data. the sum total of charact ers in mfr_id, mfr_model, mfr_revision, mfr_location, mfr_date, mfr_serial, and user_data_00 plus one b yte per command cannot exceed 128 characters. this limitation includes multiple writes of thi s command before a store command. to clear multiple writes, perform a restore, write this command then perform a st ore/restore. data length in bytes: user defined data format: asc type: block r/w default value: null units: n/a isense_config (d0h) definition: configures current sense circuitry. data length in bytes: 1 data format: bit type: r/w default value: 06h (256ns current sense blanking time, current sense high ran ge) units: n/a bit field name value setting description 7:4 reserved 0000 3:2 current sense blanking time 00 192ns sets the blanking time current sense blanking time. 01 256ns 10 412ns 11 640ns 1:0 current sense range 00 low range 25mv 01 mid range 35mv 10 high range 50mv 11 not used
fn8931 rev.1.00 page 63 of 81 jan 4, 2018 isl8274m 7. pmbus commands description user_config (d1h) definition: configures several user-level f eatures. this command overrides the pin-strap settings. data length in bytes: 1 data format: bit type: r/w default value : 84h (pin-strap setting for as cr on start up; ramp-up and ramp -down minimum duty cycle 0.39%; minimum duty cycle c ontrol enabled; pg is an open-drain output. ) units: n/a ddc_config (d3h) definition: configures ddc addressing and curr ent sharing. the ddc rail id is set according to t he smbus address. for current sharing a pplications, the ddc phase id is set accor ding to the number of phases. the device position and number of devices in the rail c an be programmed as needed. data length in bytes: 2 data format: bit type: r/w default value: pin-strap setting for rail id. ph ase id = 0; phases in rail = 1 units: n/a bit field name value setting description 7 ascr on for start up 0 disabled ascr is disabled for st art up. use this for current sh aring mode. 1 enabled ascr is enabled for star t up. use this for stand alone mode. 6:5 reserved 00 reserved 4:3 ramp-up and ramp-down minimum duty cycle 00 0.39% sets the minimum duty-cycle during start-up and shutdown ramp. 01 0.78% 10 1.17% 11 1.56% 2 minimum duty cycle control 0 disable control for mi nimum duty cycle. 1 enable 1 power-good pin configuration 0 open drain 0 = pg is an open-drain output. 1 push-pull 1 = pg is a push-pull output. 0 reserved 0 bit field name value setting description 15:13 phase id 0 to 7 sets the phase id in a current sharing rail. 12:8 rail id 0 to 31 (00 to 1fh) configures ddc rail id 7:3 reserved 0 reserved reserved 2:0 phases in rail 0 to 7 identifies the number of phases on the s ame rail (+1).
fn8931 rev.1.00 page 64 of 81 jan 4, 2018 isl8274m 7. pmbus commands description power_good_delay (d4h) definition: sets the delay applied between t he output exceeding the pg thr eshold (power_good_on) and asserting the pg pin. the delay time can range from 0ms up to 5 00s, in steps of 125ns. a 1ms minimum configured value is recommended to apply p roper debounce to this signal. data length in bytes: 2 data format: l11 type: r/w default value: c300h, 3ms units: ms range: 0ms to 5s ascr_config (dfh) definition: allows user configuration of as cr settings. ascr gain is analo gous to bandwidth, ascr residual is analogous to damping. to improve l oad transient response perfor mance, increase ascr gai n. to lower transient response overshoot, increase ascr residual. increasing ascr gai n can result in increased p wm jitter and should be evaluated in the application circ uit. excessive ascr gain can l ead to excessive output vo ltage ripple. increasing ascr residual to improve transient response damping can result in slower recovery times, bu t will not affect the peak output voltage deviation. typical ascr gain settings range from 50 to 1000, and ascr resi dual settings range from 10 to 100. data length in bytes: 4 data format: cus type: r/w default value: pin-strap setting bit purpose data format value description 31:25 unused 0000000h unused 24 ascr enable bit 1 enable 0 disable 23:16 ascr residual setting integer ascr residual 15:0 ascr gain setting integer ascr gain
fn8931 rev.1.00 page 65 of 81 jan 4, 2018 isl8274m 7. pmbus commands description sequence (e0h) definition: identifies the rail ddc id of the prequel and sequel rails whe n performing multi-rail sequencing. the device will enable its output whe n its en or operation enable s tates, as defined by on_ off_config, is set and the prequel device has issued a p ower-good event on the ddc bus . the device will disable its output (using the programmed delay values) when th e sequel device has issued a po wer-down event on the ddc bus. the data field is a two-byte val ue. the most significant byte c ontains the 5-bit rail ddc id of the prequel device. the least significant byte (lsb) con tains the 5-bit rail ddc id of the sequel device. the most significant bit (msb) of each byte contains the e nable of the prequel or sequel mode. th is command overrides the corresponding sequence configuration set by t he config pin settings. data length in bytes: 2 data format: bit type: r/w default value: 0000h (prequel and sequel disabled) bit field name value setting description 15 prequel enable 0 disable disable , no prequel preceding this rail . 1 enable enable, prequel to this rail is defined by bits 12:8. 14:13 reserved 0 reserved reserved 12:8 prequel rail ddc id 0-31 ddc id set to the ddc id of the prequel rail. 7 sequel enable 0 disable disable, no sequel following this rail. 1 enable enable, sequel to this rai l is defined by bits 4:0. 6:5 reserved 0 reserved reserved 4:0 sequel rail ddc id 0-31 ddc id set to the ddc id of the sequel rail.
fn8931 rev.1.00 page 66 of 81 jan 4, 2018 isl8274m 7. pmbus commands description track_config (e1h) definition: configures the voltage tracking modes of the device. only one channel can be configured to track: channel 1 or channel 2. data length in bytes: 1 data format: bit type: r/w default value: pin-strap setting based on ss/track ddc_group (e2h) definition: configures fault spreading grou p id and enable, broadcast oper ation group id and enable, and broadcast vout_command group id and enable. data length in bytes : 3 data format: bit type: block r/w default value: ignore broadcast vout_command, operation. bit field name value setting description 7 voltage tracking control 0 disable tracking is disabled 1 enable tracking is enabled 6:3 reserved 0000 reserved reserved 2 tracking ratio control 0 100% output tracks at 100% ratio of vtrk input 1 50% output tracks at 50% ratio of vtrk input 1 tracking upper limit 0 target voltage output voltage is limited by target voltage 1 vtrk voltage output voltage is limited by vtrk voltage 0 ramp-up behavior 0 track after pg the output is not allowed to tr ack vtrk down before power-good. 1 track always the output is allowed to track vtrk down before power-good. bits purpose value description 23:22 reserved 0 reserved 21 broadcast_vout_command response 1 responds to broadcast_vout_command with same group id. 0 ignores broadcast_vout_command. 20:16 broadcast_vout_command group id 0-31d group id sent as data for br oadcast broadcast_vout_command events. 15:14 reserved 0 reserved 13 broadcast_operation response 1 responds to broadcast_operation with same group id. 0 ignores broadcast_operation. 12:8 broadcast_operation group id 0-31d group id sent as data for broadcast broadcast_operation events. 7:6 reserved 0 reserved 5 power_fail response 1 responds to power_fail events with same gr oup id by shutting down immediately. 0 responds to power_fail events with same group id with sequence d shutdown. 4:0 power_fail group id 0-31d group id sent as data for broadcast power_fail events.
fn8931 rev.1.00 page 67 of 81 jan 4, 2018 isl8274m 7. pmbus commands description device_id (e4h) definition: returns the 16-byte (charact er) device identifier string. data length in bytes: 16 data format: asc type: block read default value: part number/die revision/firmware revision mfr_iout_oc_fault_response (e5h) definition: configures the i out overcurrent fault response as de fined by the following table. the command format is the same as the pmbus standard f ault responses except that it s ets the overcurrent status bit in status_iout. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable, and no retry) units: n/a mfr_iout_uc_fault_response (e6h) definition: configures the i out undercurrent fault response as de fined by the following table. the command format is the same as the pmbus standard f ault responses except that it s ets the undercurrent stat us bit in status_iout. data length in bytes: 1 data format: bit type: r/w default value: 80h (disable and no retry) units: n/a bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms. bit field name value description 7:6 reserved 10 5:3 retry setting 000 no retry. the output remains disabled until the fault is cleared. 001-110 not used. 111 attempts to restart continuously, without checking if the fa ult is still present, until it is commanded off (by the contro l pin or operation command), bia s power is removed, or another fault condition causes the unit to shut down. 2:0 retry delay 000-111 retry delay time = (value + 1)*35ms. sets the time between retries in 35ms increments. range is 35ms to 280ms.
fn8931 rev.1.00 page 68 of 81 jan 4, 2018 isl8274m 7. pmbus commands description iout_avg_oc_fault_limit (e7h) definition: sets the i out average overcurrent fault threshold. for down-slope sensing, t his corresponds to the average of all the current samples taken during the (1-d) time interval , excluding the current sense blanking time (which occurs at the beginning of the 1-d inte rval). for up-slope sensing, th is corresponds to the average of all the current samples taken during the d time interval, excluding the current sense b lanking time (which occurs at the beginning of the d interval). this featur e shares the oc fault bit operation (in s tatus_iout) and oc fault response with iout_oc_fault_limit. paged or global: paged data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: sync/ocp pin-strap setting units: a equation: iout_avg_oc_fault_limit = y2n range: -100a to 100a iout_avg_uc_fault_limit (e8h) definition: sets the i out average undercurrent fault thr eshold. for down-slope sensing, this corresponds to the average of all the current sampl es taken during the (1-d) time interval, excluding the curr ent sense blanking time (which occurs at the beginning of the 1-d interval). for up-slo pe sensing, this corresponds to the average of all the current samples taken during the d time interval, excluding the current sense blanking time (which occurs at the beginning of the d interval). this feature shares the uc fault bit operation (in status_iout) and uc fault response with iout_ uc_fault_limit. paged or global: paged data length in bytes: 2 data format: linear-11 type: r/w protectable: yes default value: dc40h (-30a) units: a equation: iout_avg_uc_fault_limit = y2n range: -100a to 100a
fn8931 rev.1.00 page 69 of 81 jan 4, 2018 isl8274m 7. pmbus commands description sync_config (e9h) definition: used to set options for s ync output configurations. data length in bytes: 1 data format: bit type: r/w default value: pin-strap setting snapshot (eah) definition: a 32-byte read-back of parametric and status values. it allows monitoring and status data to be stored to flash following a fault conditio n. in case of a fault, last upd ated values are st ored to the flash memory. when the snapshot status bit is set store d, device will no longer automa tically capture paramet ric and status values following fault till stored data are erased. use the snapshot_c ontrol command to erase store data and clear the status bit before next ramp up. d ata erased is not allowed when module is enabled. data length in bytes: 32 data format: bit field type: block read settings actions 00h use internal clock. clock fre quency is set by pin-strap or p mbus command. 02h use internal clock and output internal clock. 04h use external clock. byte number value pmbus command format 31:23 reserved reserved 00h 22 flash memory status byte ff - not stored 00 - stored n/a bit 21 manufacturer specific status byte status_mfr_specific (80h) byt e 20 cml status byte status_cml (7eh) byte 19 temperature status byte status_temperature (7dh) byte 18 input status byte status_input (7ch) byte 17 i out status byte status_iout (7bh) byte 16 v out status byte status_vout (7ah) byte 15:14 switching frequency read_frequency (95h) l11 13:12 reserved reserved 00h 11:10 internal temperature read_internal_temp (8dh) l11 9:8 duty cycle read_duty_cycle (94h) l11 7:6 highest measured output current n/a l11 5:4 output current read_iout (8ch) l11 3:2 output voltage read_vout (8bh) l16u 1:0 input voltage read_vin (88h) l11
fn8931 rev.1.00 page 70 of 81 jan 4, 2018 isl8274m 7. pmbus commands description blank_params (ebh) definition: returns a 16-byte string indicating which parameter values were either retrieved by the last restore operation or have been written since that time. reading blank_p arams immediately afte r a restore operation allows the user to determine whi ch parameters ar e stored in tha t store. a 1 indicates the p arameter is not present in the store and has not been writte n since the rest ore operation. data length in bytes: 16 data format: bit type: block read default value: ffffh snapshot_control (f3h) definition: writing a 01h will cause the device to copy the current snapsh ot values from nvram to the 32-byte snapshot command parameter. wri ting a 02h will cause the device to write the current snapshot values to nvram. writing a 03h will erase all sna pshot values from nvram. write (02h) and erase (03h) ma y only be used when the device is disabled. all oth er values will be ignored. data length in bytes: 1 data format: bit field type: r/w byte restore_factory (f4h) definition: restores the device to the hard coded factory default values a nd pin-strap definitions. the device retains the default and user stores for restori ng. security level is ch anged to level 1 following this command. data length in bytes: 0 data format: n/a type: send byte default value: n/a units: n/a mfr_vmon_ov_fault_limit (f5h) definition: reads the vmon ov fault threshold. data length in bytes: 2 data format: l11 type: read only default value: cb00h (6v) units: v range: 4v to 6v value description 01h read snapshot values from nv ram 02h write snapshot values to nv ram 03h erase snapshot values stored in nv ram.
fn8931 rev.1.00 page 71 of 81 jan 4, 2018 isl8274m 7. pmbus commands description mfr_vmon_uv_fault_limit (f6h) definition: reads the vmon uv fault threshold. data length in bytes: 2 data format: l11 type: read only default value: ca00h (4v) units: v range: 4v to 6v mfr_read_vmon (f7h) definition: reads the vmon voltage. data length in bytes: 2 data format: l11 type: read only default value: n/a units: v range: 4v to 6v vmon_ov_fault_response (f8h) definition: reads the vmon ov fault response. data length in bytes: 1 data format: bit type: read only default value: 80h (disable and no retry) units: n/a vmon_uv_fault_response (f9h) definition: reads the vmon uv fault respon se, which is a direct copy of vi n_uv_fault_response. data length in bytes: 1 data format: bit type: read only default value: 80h (disable and no retry) units: v
fn8931 rev.1.00 page 72 of 81 jan 4, 2018 isl8274m 8. firmware revision history 8. firmware revision history table 8. isl8274m nomenclature guide firmware revision code change description note isl8274m-0-g0100 initial release
fn8931 rev.1.00 page 73 of 81 jan 4, 2018 isl8274m 9. package outline drawing 9. package outline drawing y58.18x23 58 i/o 18mmx23mmx7.5mm custom hda module rev 3, 12/16 15 18 16 17 13 14 11 12 ab ac u v w y aa n p r t 6 9 10 7 84 52 3 h j k l m d e f g a b c 1 terminal tip 7.50 max max 0.025 seating side view c 42 x 0.60 0.05 top view 18.00 detail a 0.20 ref 0.20 ref 0.10 c (9x11.5) index area terminal #a1 0.10 c2x 2x 23.00 a b 0.10 c a b 3 3 0.05 c 42 x 0.60 0.05 2 2 1.00 1.00 0.10 c 0.08 c represents the basic land grid pitch. 3. 2. all dimensions are in millimeters. 1. notes: dimensioning and tolerancing per asme y14.5-2009. tolerance for exposed pad edge location dimension on 4. 5. these 42 i/os are centered in a fixed row and column matrix at 1.0mm pitch bsc. page 3 is 0.1mm. datum a pin a1 indicator c = 0.35 see detail a datum b 16.00 17.20 22.60 0.15 0.10 c a b m 0.40 ref 0.10 c a b m 12.00 bottom view 0.100 r ref m m plane for the most recent package outline drawing, see y58.18x23 .
fn8931 rev.1.00 page 74 of 81 jan 4, 2018 isl8274m 9. package outline drawing 9.70 2.90 3.60 2.00 5.40 7.00 4.00 6.50 8.60 0.20 0.80 6.60 7.20 2.60 8.50 6.40 2.90 5.10 2.40 1.80 4.40 4.60 6.00 0.40 8.60 6.00 8.10 9.30 9.70 11.30 3.80 3.00 1.20 8.10 9.30 11.30 5.20 6.30 6.00 4.00 3.30 0.00 9.10 6.20 7.20 2.00 5.70 5.50 6.30 6.50 8.80 7.80 2.70 2.30 1.70 1.30 0.70 0.70 1.30 1.70 2.30 5.80 5.20 4.80 4.20 3.80 3.20 9.30 8.70 5.30 4.70 3.30 4.30 3.70 2.70 0.30 0.30 7.30 6.70 9.70 11.30 7.70 2.30 1.00 8.20 6.80 2.00 5.50 6.50 9.10 7.20 9.30 4.30 4.70 5.30 5.70 3.70 0.00 0.70 1.30 7.30 6.70 7.80 8.80 9.70 7.70 6.30 11.30 6.20 4.80 4.20 3.80 3.20 1.80 2.20 2.80 5.20 5.80 0.50 0.50 2.80 2.20 1.20 0.80 0.80 1.20 0.20 0.20 1.80 1.60 (2x) 2.10 (2x) 1.10 (2x) 5.30 (2x) 5.60 7.40 6.40 1.40 (2x) 4.40 6.20 0.60 5.60 4.00 (2x) 4.20 2.00 (2x) 0.80 (2x) 2.20 1.10 5.00 (2x) 2.20 3.50 (2x) 2.60 4.80 (2x) 1.60 (2x) 1.00 (2x) 3.60 8.30 (2x) 3.40 1.00 (2x) 1.30 2.30 4.60 4.40 1.60 (2x) size details for the 16 exposed pads bottom view 1.00 (2x) terminal and pad edge details pad details
fn8931 rev.1.00 page 75 of 81 jan 4, 2018 isl8274m 9. package outline drawing 0.000 0.000 11.270 2.030 3.590 3.910 5.470 7.810 8.130 9.410 11.270 11.500 11.500 0.530 1.390 1.710 2.500 5.610 6.400 6.720 7.510 7.830 8.770 0.530 1.390 1.710 2.500 5.610 6.400 6.720 7.510 7.830 8.770 9.000 11.500 11.270 9.730 9.410 8.130 7.810 6.530 5.470 3.910 3.590 2.030 7.510 7.830 8.640 8.960 9.770 10.090 11.270 11.500 9.730 9.000 8.570 7.660 7.340 5.240 4.920 4.190 3.870 3.140 2.090 0.230 0.770 1.230 1.910 2.230 2.910 3.230 3.910 4.230 4.910 5.230 5.910 6.230 6.910 9.000 9.000 stencil opening edge position - 1 3.895 5.290 2.820 3.895 4.215 5.290 6.530 6.330 7.790 8.110 9.490 9.810 2.820 5.970 6.430 9.730 9.730 6.330 2.820 4.215 0.000 0.000 0.000 0.000 stencil opening edge position - 2 0.785 3.215 0.215 0.785 4.215 5.215 5.785 6.215 6.785 7.785 9.285 8.715 8.285 7.715 7.285 6.715 6.285 5.715 5.285 4.715 3.715 3.285 2.715 1.715 1.285 0.715 0.285 0.285 0.715 2.715 2.285 8.715 7.285 6.285 5.285 4.285 1.285 0.715 0.285 0.285 0.715 1.285 2.715 1.785 1.785 7.215 7.785 4.785 4.215 9.000 9.000 11.500 11.500 11.500 11.500 9.000 9.000 2.285 4.785 3.785 3.215 2.785 2.215 1.785 1.215 5.785 5.215 0.215 1.215 1.785 2.215 2.785 3.785 4.215 4.785 6.215 6.785 4.285 1.285 3.285 6.215 6.785 1.215 1.215 3.215 3.785 3.715 4.715 5.715 6.715 7.715 9.285 3.285 1.715 8.285 0.000 0.000 8.450 7.215 8.785 8.215 stencil potition 1 and 2
fn8931 rev.1.00 page 76 of 81 jan 4, 2018 isl8274m 9. package outline drawing 0.000 0.000 6.330 7.960 11.500 6.570 5.890 5.570 4.890 3.890 3.570 2.890 2.570 1.990 1.670 1.160 2.090 2.820 3.140 3.870 4.190 4.430 4.920 5.240 5.970 6.030 6.890 7.210 8.070 11.500 11.500 9.000 9.000 11.500 9.000 9.000 stencil opening edge position - 3 2.770 1.875 1.555 0.660 0.340 0.555 0.875 1.770 2.330 3.495 4.340 4.660 5.505 5.825 6.670 3.175 4.570 8.530 7.640 9.270 0.000 0.000 0.000 0.000 stencil opening edge position - 4 9.070 7.960 7.640 6.530 9.070 7.960 7.640 6.530 2.930 3.840 4.160 5.070 7.170 6.230 3.840 4.160 2.430 3.110 3.430 4.110 5.110 5.430 6.110 8.530 9.270 0.230 1.840 2.160 3.770 4.090 4.570 9.000 9.000 11.500 11.500 9.000 9.000 11.500 11.500 7.170 6.230 6.030 6.705 7.025 7.700 8.020 9.280 10.275 8.570 7.230 5.230 6.740 7.060 8.570 5.070 4.030 5.430 4.430 2.930 9.600 10.595 11.270 6.970 0.000 0.000 stencil position 3 and 4
fn8931 rev.1.00 page 77 of 81 jan 4, 2018 isl8274m 9. package outline drawing 0.000 0.000 stencil opening edge position - 5 6.890 8.070 1.030 2.270 4.030 2.030 3.570 4.430 4.910 8.770 7.810 7.490 6.530 0.430 1.770 6.030 6.705 7.025 7.700 3.030 4.080 4.810 5.130 5.860 6.180 6.910 9.000 9.000 9.280 9.600 10.275 10.595 11.270 11.500 11.500 9.000 9.000 11.500 11.500 5.070 6.030 7.210 3.760 8.020 0.000 pcb land pattern - 1 (for reference) 0.000 9.000 8.800 7.800 7.540 6.690 6.430 5.580 5.320 4.185 3.925 2.790 2.530 1.680 1.420 0.500 1.420 1.680 2.530 2.790 3.925 4.185 5.320 5.580 6.430 6.690 7.540 7.800 8.450 9.000 0.000 11.500 10.950 9.700 9.440 8.100 7.840 6.500 5.500 3.880 3.620 2.000 6.300 7.540 7.800 8.670 8.930 9.800 10.060 11.300 11.500 9.700 0.000 9.000 8.600 7.630 7.370 6.400 6.000 5.210 4.950 4.160 3.900 3.110 2.850 2.060 0.200 0.800 1.200 1.940 2.200 2.940 3.200 3.940 4.200 4.940 5.200 5.940 6.200 6.940 9.000 0.000 9.780 9.700 9.520 8.080 7.820 6.300 11.300 11.500 2.000 3.620 3.880 5.500 6.500 7.840 8.100 9.440 9.700 11.300 11.500 0.500 0.000 8.800 stencil position5 land pattern 1
fn8931 rev.1.00 page 78 of 81 jan 4, 2018 isl8274m 9. package outline drawing pcb land pattern - 2 (for reference) 0.000 9.000 5.800 5.200 4.800 4.200 6.800 6.200 3.800 3.200 2.800 2.200 1.800 1.200 0.800 0.200 0.200 0.800 1.200 1.800 2.200 2.800 3.200 3.800 4.200 4.800 9.000 5.200 5.800 0.000 11.500 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 1.300 0.700 0.300 0.300 0.700 1.300 2.700 3.300 11.500 0.000 9.000 4.800 4.200 3.800 3.200 1.800 1.200 0.200 0.800 1.200 1.800 3.200 3.800 4.200 4.800 6.200 6.800 7.200 7.800 9.000 0.000 11.500 9.300 8.700 8.300 7.700 7.300 6.700 6.300 5.700 5.300 4.700 4.300 3.700 3.300 2.700 2.300 1.700 1.300 0.700 0.300 0.300 0.700 1.300 2.700 3.300 11.500 6.200 6.800 7.200 7.800 8.200 8.800 1.700 2.300 pcb land pattern - 3 (for reference) 0.000 1.800 0.845 0.585 0.370 0.630 1.585 1.845 2.800 9.000 9.000 0.000 6.700 5.795 5.535 4.630 4.370 3.465 3.205 2.300 6.000 6.920 7.180 8.100 11.500 11.500 0.000 11.500 9.300 8.500 7.930 7.670 6.300 11.500 0.000 9.000 6.000 5.210 4.950 4.160 3.900 3.110 2.850 2.060 9.000 1.060 1.700 1.960 2.600 2.860 3.600 3.860 4.600 4.860 5.600 5.860 6.600 land pateer - 2 and 3
fn8931 rev.1.00 page 79 of 81 jan 4, 2018 isl8274m 9. package outline drawing pcb land pattern - 4 (for reference) 9.100 7.930 7.670 6.500 9.000 7.200 6.200 9.000 0.000 11.500 2.900 3.870 4.130 5.100 8.500 9.300 11.500 0.000 9.000 6.140 5.400 5.140 4.400 4.140 3.400 3.140 2.400 7.030 6.770 5.200 8.600 9.000 0.000 11.500 11.300 10.565 10.305 9.570 9.310 7.990 7.730 6.995 6.735 6.000 5.100 4.000 4.130 3.870 2.900 11.500 6.500 7.670 7.930 9.100 0.200 1.870 2.130 3.800 4.060 4.600 5.400 7.000 7.200 8.600 0.000 7.200 6.200 0.000 4.000 5.100 6.000 6.735 6.995 7.730 7.990 9.310 9.570 10.305 10.565 11.300 11.500 11.500 9.000 1.800 0.400 3.000 3.790 4.050 4.840 5.100 5.890 6.150 6.940 9.000 0.000 11.500 8.100 7.180 6.920 6.000 11.500 0.000 9.000 1.000 2.300 pcb land pattern - 5 (for reference) 0.000 8.800 7.780 7.520 6.500 4.940 4.400 3.600 2.000 land pateer - 4 and 5
fn8931 rev.1.00 page 80 of 81 jan 4, 2018 isl8274m 10. revision history 10. revision history rev. date description 1.00 jan 4, 2018 fixed the note numbering for table 2 on page 11. added isense_config default s etting to test conditions and up dated typical from 0.1 to 0.2 for the output current read back resol ution specification on page 13. removed about intersil sec tion and updated disclaimer. 0.00 nov 28, 2017 initial release
http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 1001 murphy ranch road, milpitas, ca 95035, u.s.a. tel: +1-408-432-8888, fax: +1-408-434-5351 renesas electronics canada limited 9251 yonge street, suite 8309 richmond hill, ontario canada l4c 9t3 tel: +1-905-237-2004 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709 quantum plaza, no.27 zhichunlu, haidian district, beijing, 100191 p. r. china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, 200333 p. r. china tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal 2nd stage, indiranagar, bangalore 560 038, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 17f, kamco yangjae tower, 262, gangnam-daero, gangnam-gu, seoul, 06265 korea tel: +82-2-558-3737, fax: +82-2-558-5338 sales offices ? 2018 renesas electronics corporation. all rights reserved. colophon 7.0 (rev.4.0-1 november 2017) notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. renesas electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims inv olving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of renesas electronics products or technical information described in this document, including but not lim ited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property ri ghts of renesas electronics or others. 4. you shall not alter, modify, copy, or reverse engineer any renesas electronics product, whether in whole or in part. renesas electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering. 5. renesas electronics products are classified according to the following two quality grades: standard and high quality. th e intended applications for each renesas electronics product depends on the products quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale com munication equipment; key financial terminal systems; safety control equipment; etc. unless expressly designated as a high reliability product or a product for harsh environments in a renesas electronics data sh eet or other renesas electronics document, renesas electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artific ial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant s ystems; military equipment; etc.). renesas electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any renesas electronics produc t that is inconsistent with any renesas electronics data sheet, users manual or other renesas electronics document. 6. when using renesas electronics products, refer to the latest product information (data sheets, users manuals, application n otes, general notes for handling and using semiconductor devices in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by renesas electronics with respe ct to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. renesas electronics disclaims any and all liability for any malfunctions, failure or accide nt arising out of the use of renesas electronics products outside of such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of renesas electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. unless designated as a high reliability product or a product for ha rsh environments in a renesas electronics data sheet or other renesas electronics document, renesas electronics products are not subject to radiation resistance design. you are responsible for impl ementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of renesas electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. you are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, includi ng without limitation, the eu rohs directive, and using renesas electronics products in compliance with all these applicable laws and regulations. renesas electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technologies shall not be used for or incorporated into any products or systems whose manuf acture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you shall comply with any applicable export control laws and regulations promulgated and administered by the go vernments of any countries asserting jurisdiction over the parties or transactions. 10. it is the responsibility of the buyer or distributor of renesas electronics products, or any other party who distributes, d isposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. this document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written cons ent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products. (note 1) renesas electronics as used in this document means renesas electronics corporation and also includes its directly o r indirectly controlled subsidiaries. (note 2) renesas electronics product(s) means any product developed or manufactured by or for renesas electronics.

▲Up To Search▲

Price & Availability of ISL8274MAIRZ

	To Download ISL8274MAIRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .